From: Nancy Lin <nancy.lin@mediatek.com>
- Add initialization of top clocks and async clocks for each MMSYS.
- Add PM runtime control and new functions to manage these clocks.
- Add functions to set these clocks according to the default
configuration of the corresponding MMSYS.
Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 152 ++++++++++++++++++++++++-
drivers/soc/mediatek/mtk-mmsys.h | 18 +++
include/linux/soc/mediatek/mtk-mmsys.h | 8 ++
3 files changed, 177 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index bb4639ca0b8c..f448cc09ce19 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,12 +4,15 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/bitfield.h>
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
@@ -158,6 +161,9 @@ struct mtk_mmsys {
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
struct cmdq_client_reg cmdq_base;
+ struct clk **async_clk;
+ int num_async_clk;
+ struct clk **top_clk;
};
static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
@@ -180,6 +186,101 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask,
writel_relaxed(tmp, mmsys->regs + offset);
}
+int mtk_mmsys_top_clk_enable(struct device *dev)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ int ret, i;
+
+ if (!mmsys->data->num_top_clk)
+ return 0;
+
+ for (i = 0; i < mmsys->data->num_top_clk; i++)
+ ret = clk_prepare_enable(mmsys->top_clk[i]);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_top_clk_enable);
+
+void mtk_mmsys_top_clk_disable(struct device *dev)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < mmsys->data->num_top_clk; i++)
+ clk_disable_unprepare(mmsys->top_clk[i]);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_top_clk_disable);
+
+int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
+
+ int i;
+
+ if (!mmsys->data->num_async_info)
+ return 0;
+
+ for (i = 0; i < mmsys->data->num_async_info; i++)
+ if (comp_id == async[i].comp_id)
+ return clk_prepare_enable(mmsys->async_clk[async[i].index]);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_enable);
+
+void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
+ int i;
+
+ if (!mmsys->data->num_async_info)
+ return;
+
+ for (i = 0; i < mmsys->data->num_async_info; i++)
+ if (comp_id == async[i].comp_id)
+ clk_disable_unprepare(mmsys->async_clk[async[i].index]);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_disable);
+
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id,
+ int width, int height, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
+ int i;
+ u32 val;
+
+ if (!mmsys->data->num_async_info)
+ return;
+
+ for (i = 0; i < mmsys->data->num_async_info; i++)
+ if (comp_id == async[i].comp_id)
+ break;
+
+ if (i == mmsys->data->num_async_info)
+ return;
+
+ val = FIELD_PREP(GENMASK(31, 16), height);
+ val |= FIELD_PREP(GENMASK(15, 0), width);
+ mtk_mmsys_update_bits(mmsys, async[i].offset, async[i].mask, val, cmdq_pkt);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
+void mtk_mmsys_default_config(struct device *dev)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_default *def_config = mmsys->data->def_config;
+ int i;
+
+ if (!mmsys->data->num_def_config)
+ return;
+
+ for (i = 0; i < mmsys->data->num_def_config; i++)
+ mtk_mmsys_update_bits(mmsys, def_config[i].offset, def_config[i].mask,
+ def_config[i].val, NULL);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_default_config);
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -390,7 +491,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
- int ret;
+ int ret, i;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
if (!mmsys)
@@ -432,6 +533,49 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return PTR_ERR(clks);
mmsys->clks_pdev = clks;
+ if (mmsys->data->num_top_clk) {
+ struct device_node *node;
+
+ node = of_get_child_by_name(dev->of_node, "top");
+ if (!node) {
+ dev_err(&pdev->dev, "Couldn't find top node\n");
+ return -EINVAL;
+ }
+
+ mmsys->top_clk = devm_kmalloc_array(dev, mmsys->data->num_top_clk,
+ sizeof(*mmsys->top_clk), GFP_KERNEL);
+ if (!mmsys->top_clk)
+ return -ENOMEM;
+
+ for (i = 0; i < mmsys->data->num_top_clk; i++) {
+ mmsys->top_clk[i] = of_clk_get(node, i);
+ if (IS_ERR(mmsys->top_clk[i]))
+ return PTR_ERR(mmsys->top_clk[i]);
+ }
+ }
+
+ if (mmsys->data->num_async_info) {
+ struct device_node *node;
+
+ node = of_get_child_by_name(dev->of_node, "async");
+ if (!node) {
+ dev_err(&pdev->dev, "Couldn't find async node\n");
+ return -EINVAL;
+ }
+
+ mmsys->async_clk = devm_kmalloc_array(dev, mmsys->data->num_async_info,
+ sizeof(*mmsys->async_clk), GFP_KERNEL);
+ if (!mmsys->async_clk)
+ return -ENOMEM;
+ mmsys->num_async_clk = mmsys->data->num_async_info;
+
+ for (i = 0; i < mmsys->num_async_clk; i++) {
+ mmsys->async_clk[i] = of_clk_get(node, i);
+ if (IS_ERR(mmsys->async_clk[i]))
+ return PTR_ERR(mmsys->async_clk[i]);
+ }
+ }
+
if (mmsys->data->is_vppsys)
goto out_probe_done;
@@ -443,6 +587,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->drm_pdev = drm;
+ if (of_property_present(dev->of_node, "power-domains"))
+ pm_runtime_enable(dev);
+
out_probe_done:
return 0;
}
@@ -453,6 +600,9 @@ static void mtk_mmsys_remove(struct platform_device *pdev)
platform_device_unregister(mmsys->drm_pdev);
platform_device_unregister(mmsys->clks_pdev);
+
+ if (of_property_present(pdev->dev.of_node, "power-domains"))
+ pm_runtime_disable(&pdev->dev);
}
static const struct of_device_id of_match_mtk_mmsys[] = {
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index fe628d5f5198..bbc03ef5b025 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -102,6 +102,19 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_async_info {
+ u32 comp_id;
+ u32 index;
+ u32 offset;
+ u32 mask;
+};
+
+struct mtk_mmsys_default {
+ u32 offset;
+ u32 val;
+ u32 mask;
+};
+
/**
* struct mtk_mmsys_driver_data - Settings of the mmsys
* @clk_driver: Clock driver name that the mmsys is using
@@ -139,6 +152,11 @@ struct mtk_mmsys_driver_data {
const u32 num_resets;
const bool is_vppsys;
const u8 vsync_len;
+ const struct mtk_mmsys_async_info *async_info;
+ const unsigned int num_async_info;
+ const struct mtk_mmsys_default *def_config;
+ const unsigned int num_def_config;
+ const unsigned int num_top_clk;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4885b065b849..f50f626e1840 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -84,6 +84,14 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+int mtk_mmsys_top_clk_enable(struct device *dev);
+void mtk_mmsys_top_clk_disable(struct device *dev);
+int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id);
+void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id,
+ int width, int height, struct cmdq_pkt *cmdq_pkt);
+void mtk_mmsys_default_config(struct device *dev);
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
--
2.45.2On Thu, 2025-08-28 at 16:07 +0800, Paul Chen wrote:
> From: Nancy Lin <nancy.lin@mediatek.com>
>
> - Add initialization of top clocks and async clocks for each MMSYS.
> - Add PM runtime control and new functions to manage these clocks.
> - Add functions to set these clocks according to the default
> configuration of the corresponding MMSYS.
This patch include 3 things:
1. Add runtime PM
2. top clock control
3. async control
I would like you to separate these to different patch.
>
> Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> ---
[snip]
> +
> +int mtk_mmsys_ddp_clk_enable(struct device *dev, enum mtk_ddp_comp_id comp_id)
This is to control async clock, so change the function name to
mtk_mmsys_async_clk_enable()
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
> +
> + int i;
> +
> + if (!mmsys->data->num_async_info)
for-loop would check this, so drop this.
> + return 0;
> +
> + for (i = 0; i < mmsys->data->num_async_info; i++)
> + if (comp_id == async[i].comp_id)
> + return clk_prepare_enable(mmsys->async_clk[async[i].index]);
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_enable);
> +
> +void mtk_mmsys_ddp_clk_disable(struct device *dev, enum mtk_ddp_comp_id comp_id)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
> + int i;
> +
> + if (!mmsys->data->num_async_info)
for-loop would check this, so drop this.
> + return;
> +
> + for (i = 0; i < mmsys->data->num_async_info; i++)
> + if (comp_id == async[i].comp_id)
> + clk_disable_unprepare(mmsys->async_clk[async[i].index]);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_disable);
> +
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id comp_id,
> + int width, int height, struct cmdq_pkt *cmdq_pkt)
This is to control async. So change the function name to
mtk_mmsys_async_config()
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_async_info *async = mmsys->data->async_info;
> + int i;
> + u32 val;
> +
> + if (!mmsys->data->num_async_info)
If mmsys->data->num_async_info = 0, then i = 0, and it would return below.
So this checking is redundant.
> + return;
> +
> + for (i = 0; i < mmsys->data->num_async_info; i++)
> + if (comp_id == async[i].comp_id)
> + break;
> +
> + if (i == mmsys->data->num_async_info)
> + return;
> +
> + val = FIELD_PREP(GENMASK(31, 16), height);
> + val |= FIELD_PREP(GENMASK(15, 0), width);
> + mtk_mmsys_update_bits(mmsys, async[i].offset, async[i].mask, val, cmdq_pkt);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> +
> +void mtk_mmsys_default_config(struct device *dev)
Why not do this when mmsys probe?
Regards,
CK
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_default *def_config = mmsys->data->def_config;
> + int i;
> +
> + if (!mmsys->data->num_def_config)
> + return;
> +
> + for (i = 0; i < mmsys->data->num_def_config; i++)
> + mtk_mmsys_update_bits(mmsys, def_config[i].offset, def_config[i].mask,
> + def_config[i].val, NULL);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_default_config);
> +
On Tue, 2025-09-16 at 03:03 +0000, CK Hu (胡俊光) wrote:
> On Thu, 2025-08-28 at 16:07 +0800, Paul Chen wrote:
> > From: Nancy Lin <nancy.lin@mediatek.com>
> >
> > - Add initialization of top clocks and async clocks for each MMSYS.
> > - Add PM runtime control and new functions to manage these clocks.
> > - Add functions to set these clocks according to the default
> > configuration of the corresponding MMSYS.
>
> This patch include 3 things:
> 1. Add runtime PM
> 2. top clock control
> 3. async control
>
> I would like you to separate these to different patch.
>
> >
> > Sure I will seperate it to three different patch.
> > Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> > Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> > ---
>
> [snip]
>
> > +
> > +int mtk_mmsys_ddp_clk_enable(struct device *dev, enum
> > mtk_ddp_comp_id comp_id)
>
> This is to control async clock, so change the function name to
>
> mtk_mmsys_async_clk_enable()
>
>
> OK Got it.
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_async_info *async = mmsys->data-
> > >async_info;
> > +
> > + int i;
> > +
> > + if (!mmsys->data->num_async_info)
>
> for-loop would check this, so drop this.
>
Sure, I will drop this condition check.
> > + return 0;
> > +
> > + for (i = 0; i < mmsys->data->num_async_info; i++)
> > + if (comp_id == async[i].comp_id)
> > + return clk_prepare_enable(mmsys-
> > >async_clk[async[i].index]);
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_enable);
> > +
> > +void mtk_mmsys_ddp_clk_disable(struct device *dev, enum
> > mtk_ddp_comp_id comp_id)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_async_info *async = mmsys->data-
> > >async_info;
> > + int i;
> > +
> > + if (!mmsys->data->num_async_info)
>
> for-loop would check this, so drop this.
>
> Sure, I will drop this condition check.
>
> > + return;
> > +
> > + for (i = 0; i < mmsys->data->num_async_info; i++)
> > + if (comp_id == async[i].comp_id)
> > + clk_disable_unprepare(mmsys-
> > >async_clk[async[i].index]);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_clk_disable);
> > +
> > +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_ddp_comp_id
> > comp_id,
> > + int width, int height, struct cmdq_pkt
> > *cmdq_pkt)
>
> This is to control async. So change the function name to
>
> mtk_mmsys_async_config()
>
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_async_info *async = mmsys->data-
> > >async_info;
> > + int i;
> > + u32 val;
> > +
> > + if (!mmsys->data->num_async_info)
>
> If mmsys->data->num_async_info = 0, then i = 0, and it would return
> below.
> So this checking is redundant.
>
> > + return;
> > +
> > + for (i = 0; i < mmsys->data->num_async_info; i++)
> > + if (comp_id == async[i].comp_id)
> > + break;
> > +
> > + if (i == mmsys->data->num_async_info)
> > + return;
> > +
> > + val = FIELD_PREP(GENMASK(31, 16), height);
> > + val |= FIELD_PREP(GENMASK(15, 0), width);
> > + mtk_mmsys_update_bits(mmsys, async[i].offset,
> > async[i].mask, val, cmdq_pkt);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > +
> > +void mtk_mmsys_default_config(struct device *dev)
>
> Why not do this when mmsys probe?
>
>
> The mtk_mmsys_default_config is also using at DP Suspnd /Resume.
Hence, we need to keep the default config setting at here.
Best, Paul-pl Chen
>
>
>
> Regards,
> CK
>
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_default *def_config = mmsys->data-
> > >def_config;
> > + int i;
> > +
> > + if (!mmsys->data->num_def_config)
> > + return;
> > +
> > + for (i = 0; i < mmsys->data->num_def_config; i++)
> > + mtk_mmsys_update_bits(mmsys, def_config[i].offset,
> > def_config[i].mask,
> > + def_config[i].val, NULL);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_default_config);
> > +
>
>
On Thu, 2025-08-28 at 16:07 +0800, Paul Chen wrote:
> From: Nancy Lin <nancy.lin@mediatek.com>
>
> - Add initialization of top clocks and async clocks for each MMSYS.
> - Add PM runtime control and new functions to manage these clocks.
> - Add functions to set these clocks according to the default
> configuration of the corresponding MMSYS.
>
> Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> ---
[snip]
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -390,7 +491,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> struct platform_device *clks;
> struct platform_device *drm;
> struct mtk_mmsys *mmsys;
> - int ret;
> + int ret, i;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> if (!mmsys)
> @@ -432,6 +533,49 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return PTR_ERR(clks);
> mmsys->clks_pdev = clks;
>
> + if (mmsys->data->num_top_clk) {
> + struct device_node *node;
> +
> + node = of_get_child_by_name(dev->of_node, "top");
You should define this in binding document.
> + if (!node) {
> + dev_err(&pdev->dev, "Couldn't find top node\n");
> + return -EINVAL;
> + }
> +
> + mmsys->top_clk = devm_kmalloc_array(dev, mmsys->data->num_top_clk,
> + sizeof(*mmsys->top_clk), GFP_KERNEL);
> + if (!mmsys->top_clk)
> + return -ENOMEM;
> +
> + for (i = 0; i < mmsys->data->num_top_clk; i++) {
> + mmsys->top_clk[i] = of_clk_get(node, i);
> + if (IS_ERR(mmsys->top_clk[i]))
> + return PTR_ERR(mmsys->top_clk[i]);
> + }
> + }
> +
> + if (mmsys->data->num_async_info) {
> + struct device_node *node;
> +
> + node = of_get_child_by_name(dev->of_node, "async");
You should define this in binding document.
Regards,
CK
> + if (!node) {
> + dev_err(&pdev->dev, "Couldn't find async node\n");
> + return -EINVAL;
> + }
> +
> + mmsys->async_clk = devm_kmalloc_array(dev, mmsys->data->num_async_info,
> + sizeof(*mmsys->async_clk), GFP_KERNEL);
> + if (!mmsys->async_clk)
> + return -ENOMEM;
> + mmsys->num_async_clk = mmsys->data->num_async_info;
> +
> + for (i = 0; i < mmsys->num_async_clk; i++) {
> + mmsys->async_clk[i] = of_clk_get(node, i);
> + if (IS_ERR(mmsys->async_clk[i]))
> + return PTR_ERR(mmsys->async_clk[i]);
> + }
> + }
> +
> if (mmsys->data->is_vppsys)
> goto out_probe_done;
>
> @@ -443,6 +587,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> }
> mmsys->drm_pdev = drm;
>
> + if (of_property_present(dev->of_node, "power-domains"))
> + pm_runtime_enable(dev);
> +
> out_probe_done:
> return 0;
> }
>
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