The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 9de196f519a505cf104216d6f1d8688570dacca4
Gitweb: https://git.kernel.org/tip/9de196f519a505cf104216d6f1d8688570dacca4
Author: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
AuthorDate: Thu, 28 Aug 2025 16:42:13 +05:30
Committer: Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Mon, 01 Sep 2025 12:49:25 +02:00
x86/apic: Add support to send NMI IPI for Secure AVIC
Secure AVIC introduces a new field in the APIC backing page "NmiReq" that has
to be set by the guest to request a NMI IPI through APIC_ICR write.
Add support to set NmiReq appropriately to send NMI IPI.
Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com>
Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com>
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828111213.208933-1-Neeraj.Upadhyay@amd.com
---
arch/x86/kernel/apic/x2apic_savic.c | 26 +++++++++++++++++---------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index bdefe4c..8ed56e8 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -133,12 +133,15 @@ static inline void self_ipi_reg_write(unsigned int vector)
native_apic_msr_write(APIC_SELF_IPI, vector);
}
-static void send_ipi_dest(unsigned int cpu, unsigned int vector)
+static void send_ipi_dest(unsigned int cpu, unsigned int vector, bool nmi)
{
- update_vector(cpu, APIC_IRR, vector, true);
+ if (nmi)
+ apic_set_reg(per_cpu_ptr(savic_page, cpu), SAVIC_NMI_REQ, 1);
+ else
+ update_vector(cpu, APIC_IRR, vector, true);
}
-static void send_ipi_allbut(unsigned int vector)
+static void send_ipi_allbut(unsigned int vector, bool nmi)
{
unsigned int cpu, src_cpu;
@@ -149,14 +152,17 @@ static void send_ipi_allbut(unsigned int vector)
for_each_cpu(cpu, cpu_online_mask) {
if (cpu == src_cpu)
continue;
- send_ipi_dest(cpu, vector);
+ send_ipi_dest(cpu, vector, nmi);
}
}
-static inline void self_ipi(unsigned int vector)
+static inline void self_ipi(unsigned int vector, bool nmi)
{
u32 icr_low = APIC_SELF_IPI | vector;
+ if (nmi)
+ icr_low |= APIC_DM_NMI;
+
native_x2apic_icr_write(icr_low, 0);
}
@@ -164,22 +170,24 @@ static void savic_icr_write(u32 icr_low, u32 icr_high)
{
unsigned int dsh, vector;
u64 icr_data;
+ bool nmi;
dsh = icr_low & APIC_DEST_ALLBUT;
vector = icr_low & APIC_VECTOR_MASK;
+ nmi = ((icr_low & APIC_DM_FIXED_MASK) == APIC_DM_NMI);
switch (dsh) {
case APIC_DEST_SELF:
- self_ipi(vector);
+ self_ipi(vector, nmi);
break;
case APIC_DEST_ALLINC:
- self_ipi(vector);
+ self_ipi(vector, nmi);
fallthrough;
case APIC_DEST_ALLBUT:
- send_ipi_allbut(vector);
+ send_ipi_allbut(vector, nmi);
break;
default:
- send_ipi_dest(icr_high, vector);
+ send_ipi_dest(icr_high, vector, nmi);
break;
}