On Thu, Aug 28, 2025 at 11:14:41AM +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
>
> The driver currently supports multiple chip-selects, but only sets the
> polarity for the first one (CS 0). Fix it by setting the PCSPOL bit for
> the desired chip-select.
>
> Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver")
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/spi/spi-fsl-lpspi.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
> index eaa6bade61a6..5ea4a306ffa6 100644
> --- a/drivers/spi/spi-fsl-lpspi.c
> +++ b/drivers/spi/spi-fsl-lpspi.c
> @@ -5,6 +5,7 @@
> // Copyright 2016 Freescale Semiconductor, Inc.
> // Copyright 2018, 2023, 2025 NXP
>
> +#include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/completion.h>
> #include <linux/delay.h>
> @@ -70,7 +71,7 @@
> #define DER_TDDE BIT(0)
> #define CFGR1_PCSCFG BIT(27)
> #define CFGR1_PINCFG (BIT(24)|BIT(25))
> -#define CFGR1_PCSPOL BIT(8)
> +#define CFGR1_PCSPOL_MASK GENMASK(11, 8)
> #define CFGR1_NOSTALL BIT(3)
> #define CFGR1_HOST BIT(0)
> #define FSR_TXCOUNT (0xFF)
> @@ -423,7 +424,9 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
> else
> temp = CFGR1_PINCFG;
> if (fsl_lpspi->config.mode & SPI_CS_HIGH)
> - temp |= CFGR1_PCSPOL;
> + temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
> + BIT(fsl_lpspi->config.chip_select));
> +
> writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
>
> temp = readl(fsl_lpspi->base + IMX7ULP_CR);
>
> --
> 2.34.1
>