Add PCIe controller and PHY nodes which supports data rates of 8GT/s
and x2 lane.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 180 ++++++++++++++++++++++++++++++++++-
1 file changed, 179 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 4643705021c6ca095a16d8d7cc3adac920b21e82..b47668a64bcead3e48f58eeb2e41c04660493cb7 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -631,7 +631,7 @@ gcc: clock-controller@100000 {
clocks = <&bi_tcxo_div2>,
<0>,
<&sleep_clk>,
- <0>,
+ <&pcie0_phy>,
<0>,
<0>,
<0>,
@@ -3304,6 +3304,184 @@ gic_its: msi-controller@16040000 {
};
};
+ pcie0: pcie@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf1d>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x1000>,
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01C03000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>,
+ <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <0>;
+
+ msi-map = <0x0 &gic_its 0x1400 0x1>,
+ <0x100 &gic_its 0x1401 0x1>;
+ msi-map-mask = <0xff00>;
+
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ operating-points-v2 = <&pcie0_opp_table>;
+
+ status = "disabled";
+
+ pcie0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ };
+
+ pcieport0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ phys = <&pcie0_phy>;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c06000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,sm8750-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
--
2.34.1On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
> and x2 lane.
>
I tried to boot the upstream kernel (next-20250925 defconfig) on my
Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
is crashing during boot as PCIe is being probed.
Is this a known problem? Is there any workaround/changes in flight that
I'm missing?
Regards,
Bjorn
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 180 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 179 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 4643705021c6ca095a16d8d7cc3adac920b21e82..b47668a64bcead3e48f58eeb2e41c04660493cb7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -631,7 +631,7 @@ gcc: clock-controller@100000 {
> clocks = <&bi_tcxo_div2>,
> <0>,
> <&sleep_clk>,
> - <0>,
> + <&pcie0_phy>,
> <0>,
> <0>,
> <0>,
> @@ -3304,6 +3304,184 @@ gic_its: msi-controller@16040000 {
> };
> };
>
> + pcie0: pcie@1c00000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
> + reg = <0x0 0x01c00000 0x0 0x3000>,
> + <0x0 0x40000000 0x0 0xf1d>,
> + <0x0 0x40000f20 0x0 0xa8>,
> + <0x0 0x40001000 0x0 0x1000>,
> + <0x0 0x40100000 0x0 0x100000>,
> + <0x0 0x01C03000 0x0 0x1000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>,
> + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>;
> + bus-range = <0x00 0xff>;
> +
> + dma-coherent;
> +
> + linux,pci-domain = <0>;
> +
> + msi-map = <0x0 &gic_its 0x1400 0x1>,
> + <0x100 &gic_its 0x1401 0x1>;
> + msi-map-mask = <0xff00>;
> +
> + num-lanes = <2>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7",
> + "global";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "noc_aggr",
> + "cnoc_sf_axi";
> +
> + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "pcie-mem",
> + "cpu-pcie";
> +
> + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> + <0x100 &apps_smmu 0x1401 0x1>;
> +
> + resets = <&gcc GCC_PCIE_0_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc GCC_PCIE_0_GDSC>;
> +
> + operating-points-v2 = <&pcie0_opp_table>;
> +
> + status = "disabled";
> +
> + pcie0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* GEN 1 x1 */
> + opp-2500000 {
> + opp-hz = /bits/ 64 <2500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <250000 1>;
> + };
> +
> + /* GEN 1 x2 and GEN 2 x1 */
> + opp-5000000 {
> + opp-hz = /bits/ 64 <5000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <500000 1>;
> + };
> +
> + /* GEN 2 x2 */
> + opp-10000000 {
> + opp-hz = /bits/ 64 <10000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1000000 1>;
> + };
> +
> + /* GEN 3 x1 */
> + opp-8000000 {
> + opp-hz = /bits/ 64 <8000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <984500 1>;
> + };
> +
> + /* GEN 3 x2 */
> + opp-16000000 {
> + opp-hz = /bits/ 64 <16000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <1969000 1>;
> + };
> +
> + };
> +
> + pcieport0: pcie@0 {
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + phys = <&pcie0_phy>;
> + };
> + };
> +
> + pcie0_phy: phy@1c06000 {
> + compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
> + reg = <0 0x01c06000 0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_0_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe";
> +
> + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> + reset-names = "phy";
> +
> + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie0_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> ufs_mem_phy: phy@1d80000 {
> compatible = "qcom,sm8750-qmp-ufs-phy";
> reg = <0x0 0x01d80000 0x0 0x2000>;
>
> --
> 2.34.1
>
On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
>> and x2 lane.
>>
>
> I tried to boot the upstream kernel (next-20250925 defconfig) on my
> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
> is crashing during boot as PCIe is being probed.
>
> Is this a known problem? Is there any workaround/changes in flight that
> I'm missing?
>
Hi Bjorn,
we need this fix for the PCIe to work properly. Please try it once.
https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/
- Krishna Chaitanya.
> Regards,
> Bjorn
>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 180 ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 179 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index 4643705021c6ca095a16d8d7cc3adac920b21e82..b47668a64bcead3e48f58eeb2e41c04660493cb7 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -631,7 +631,7 @@ gcc: clock-controller@100000 {
>> clocks = <&bi_tcxo_div2>,
>> <0>,
>> <&sleep_clk>,
>> - <0>,
>> + <&pcie0_phy>,
>> <0>,
>> <0>,
>> <0>,
>> @@ -3304,6 +3304,184 @@ gic_its: msi-controller@16040000 {
>> };
>> };
>>
>> + pcie0: pcie@1c00000 {
>> + device_type = "pci";
>> + compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
>> + reg = <0x0 0x01c00000 0x0 0x3000>,
>> + <0x0 0x40000000 0x0 0xf1d>,
>> + <0x0 0x40000f20 0x0 0xa8>,
>> + <0x0 0x40001000 0x0 0x1000>,
>> + <0x0 0x40100000 0x0 0x100000>,
>> + <0x0 0x01C03000 0x0 0x1000>;
>> + reg-names = "parf",
>> + "dbi",
>> + "elbi",
>> + "atu",
>> + "config",
>> + "mhi";
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
>> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>,
>> + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>;
>> + bus-range = <0x00 0xff>;
>> +
>> + dma-coherent;
>> +
>> + linux,pci-domain = <0>;
>> +
>> + msi-map = <0x0 &gic_its 0x1400 0x1>,
>> + <0x100 &gic_its 0x1401 0x1>;
>> + msi-map-mask = <0xff00>;
>> +
>> + num-lanes = <2>;
>> +
>> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "msi0",
>> + "msi1",
>> + "msi2",
>> + "msi3",
>> + "msi4",
>> + "msi5",
>> + "msi6",
>> + "msi7",
>> + "global";
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
>> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
>> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
>> + clock-names = "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a",
>> + "ddrss_sf_tbu",
>> + "noc_aggr",
>> + "cnoc_sf_axi";
>> +
>> + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "pcie-mem",
>> + "cpu-pcie";
>> +
>> + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
>> + <0x100 &apps_smmu 0x1401 0x1>;
>> +
>> + resets = <&gcc GCC_PCIE_0_BCR>;
>> + reset-names = "pci";
>> +
>> + power-domains = <&gcc GCC_PCIE_0_GDSC>;
>> +
>> + operating-points-v2 = <&pcie0_opp_table>;
>> +
>> + status = "disabled";
>> +
>> + pcie0_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + /* GEN 1 x1 */
>> + opp-2500000 {
>> + opp-hz = /bits/ 64 <2500000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <250000 1>;
>> + };
>> +
>> + /* GEN 1 x2 and GEN 2 x1 */
>> + opp-5000000 {
>> + opp-hz = /bits/ 64 <5000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <500000 1>;
>> + };
>> +
>> + /* GEN 2 x2 */
>> + opp-10000000 {
>> + opp-hz = /bits/ 64 <10000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <1000000 1>;
>> + };
>> +
>> + /* GEN 3 x1 */
>> + opp-8000000 {
>> + opp-hz = /bits/ 64 <8000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <984500 1>;
>> + };
>> +
>> + /* GEN 3 x2 */
>> + opp-16000000 {
>> + opp-hz = /bits/ 64 <16000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <1969000 1>;
>> + };
>> +
>> + };
>> +
>> + pcieport0: pcie@0 {
>> + device_type = "pci";
>> + reg = <0x0 0x0 0x0 0x0 0x0>;
>> + bus-range = <0x01 0xff>;
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges;
>> + phys = <&pcie0_phy>;
>> + };
>> + };
>> +
>> + pcie0_phy: phy@1c06000 {
>> + compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
>> + reg = <0 0x01c06000 0 0x2000>;
>> +
>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
>> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
>> + <&gcc GCC_PCIE_0_PIPE_CLK>;
>> + clock-names = "aux",
>> + "cfg_ahb",
>> + "ref",
>> + "rchng",
>> + "pipe";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
>> + assigned-clock-rates = <100000000>;
>> +
>> + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>> + reset-names = "phy";
>> +
>> + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
>> +
>> + #clock-cells = <0>;
>> + clock-output-names = "pcie0_pipe_clk";
>> +
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> ufs_mem_phy: phy@1d80000 {
>> compatible = "qcom,sm8750-qmp-ufs-phy";
>> reg = <0x0 0x01d80000 0x0 0x2000>;
>>
>> --
>> 2.34.1
>>
On 10/8/25 6:41 AM, Krishna Chaitanya Chundru wrote: > > > On 10/2/2025 5:07 AM, Bjorn Andersson wrote: >> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote: >>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s >>> and x2 lane. >>> >> >> I tried to boot the upstream kernel (next-20250925 defconfig) on my >> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device >> is crashing during boot as PCIe is being probed. >> >> Is this a known problem? Is there any workaround/changes in flight that >> I'm missing? >> > Hi Bjorn, > > we need this fix for the PCIe to work properly. Please try it once. > https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/ This surely shouldn't cause/fix any issues, no? Konrad
On 10/8/25 10:00 AM, Konrad Dybcio wrote:
> On 10/8/25 6:41 AM, Krishna Chaitanya Chundru wrote:
>>
>>
>> On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
>>> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
>>>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
>>>> and x2 lane.
>>>>
>>>
>>> I tried to boot the upstream kernel (next-20250925 defconfig) on my
>>> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
>>> is crashing during boot as PCIe is being probed.
>>>
>>> Is this a known problem? Is there any workaround/changes in flight that
>>> I'm missing?
>>>
>> Hi Bjorn,
>>
>> we need this fix for the PCIe to work properly. Please try it once.
>> https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/
>
> This surely shouldn't cause/fix any issues, no?
Apparently this is a real fix, because sm8750.dtsi defines the PCIe
PHY under a port node, while the MTP DT assigns perst-gpios to the RC
node, which the legacy binding ("everything under the RC node") parsing
code can't cope with (please mention that in the commit message, Krishna)
And I couldn't come up with a way to describe "either both are required
if any is present under the RC node or none are allowed" in yaml
Konrad
On Wed, Oct 08, 2025 at 11:11:43AM +0200, Konrad Dybcio wrote:
> On 10/8/25 10:00 AM, Konrad Dybcio wrote:
> > On 10/8/25 6:41 AM, Krishna Chaitanya Chundru wrote:
> >>
> >>
> >> On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
> >>> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
> >>>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
> >>>> and x2 lane.
> >>>>
> >>>
> >>> I tried to boot the upstream kernel (next-20250925 defconfig) on my
> >>> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
> >>> is crashing during boot as PCIe is being probed.
> >>>
> >>> Is this a known problem? Is there any workaround/changes in flight that
> >>> I'm missing?
> >>>
> >> Hi Bjorn,
> >>
> >> we need this fix for the PCIe to work properly. Please try it once.
> >> https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/
> >
> > This surely shouldn't cause/fix any issues, no?
>
> Apparently this is a real fix, because sm8750.dtsi defines the PCIe
> PHY under a port node, while the MTP DT assigns perst-gpios to the RC
> node, which the legacy binding ("everything under the RC node") parsing
> code can't cope with (please mention that in the commit message, Krishna)
>
> And I couldn't come up with a way to describe "either both are required
> if any is present under the RC node or none are allowed" in yaml
What about:
oneOf:
- required:
- foo
- bar
- properties:
foo: false
bar: false
--
With best wishes
Dmitry
On 10/8/25 9:08 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 08, 2025 at 11:11:43AM +0200, Konrad Dybcio wrote:
>> On 10/8/25 10:00 AM, Konrad Dybcio wrote:
>>> On 10/8/25 6:41 AM, Krishna Chaitanya Chundru wrote:
>>>>
>>>>
>>>> On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
>>>>> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
>>>>>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
>>>>>> and x2 lane.
>>>>>>
>>>>>
>>>>> I tried to boot the upstream kernel (next-20250925 defconfig) on my
>>>>> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
>>>>> is crashing during boot as PCIe is being probed.
>>>>>
>>>>> Is this a known problem? Is there any workaround/changes in flight that
>>>>> I'm missing?
>>>>>
>>>> Hi Bjorn,
>>>>
>>>> we need this fix for the PCIe to work properly. Please try it once.
>>>> https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/
>>>
>>> This surely shouldn't cause/fix any issues, no?
>>
>> Apparently this is a real fix, because sm8750.dtsi defines the PCIe
>> PHY under a port node, while the MTP DT assigns perst-gpios to the RC
>> node, which the legacy binding ("everything under the RC node") parsing
>> code can't cope with (please mention that in the commit message, Krishna)
>>
>> And I couldn't come up with a way to describe "either both are required
>> if any is present under the RC node or none are allowed" in yaml
>
> What about:
>
> oneOf:
> - required:
> - foo
> - bar
> - properties:
> foo: false
> bar: false
Oh yeah, this works.. would you mind submitting a patch like this, with a
# These properties must either both be under the RC node or both under the port node
or so?
Konrad>
On Thu, Oct 09, 2025 at 10:35:52AM +0200, Konrad Dybcio wrote:
> On 10/8/25 9:08 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 08, 2025 at 11:11:43AM +0200, Konrad Dybcio wrote:
> >> On 10/8/25 10:00 AM, Konrad Dybcio wrote:
> >>> On 10/8/25 6:41 AM, Krishna Chaitanya Chundru wrote:
> >>>>
> >>>>
> >>>> On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
> >>>>> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
> >>>>>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
> >>>>>> and x2 lane.
> >>>>>>
> >>>>>
> >>>>> I tried to boot the upstream kernel (next-20250925 defconfig) on my
> >>>>> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
> >>>>> is crashing during boot as PCIe is being probed.
> >>>>>
> >>>>> Is this a known problem? Is there any workaround/changes in flight that
> >>>>> I'm missing?
> >>>>>
> >>>> Hi Bjorn,
> >>>>
> >>>> we need this fix for the PCIe to work properly. Please try it once.
> >>>> https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/
> >>>
> >>> This surely shouldn't cause/fix any issues, no?
> >>
> >> Apparently this is a real fix, because sm8750.dtsi defines the PCIe
> >> PHY under a port node, while the MTP DT assigns perst-gpios to the RC
> >> node, which the legacy binding ("everything under the RC node") parsing
> >> code can't cope with (please mention that in the commit message, Krishna)
> >>
> >> And I couldn't come up with a way to describe "either both are required
> >> if any is present under the RC node or none are allowed" in yaml
> >
> > What about:
> >
> > oneOf:
> > - required:
> > - foo
> > - bar
> > - properties:
> > foo: false
> > bar: false
>
> Oh yeah, this works.. would you mind submitting a patch like this, with a
I'd prefer it it comes from somebody who is actually working on PCIe so
that the explanations are not ridiculous. Mani?
>
> # These properties must either both be under the RC node or both under the port node
>
> or so?
>
> Konrad>
--
With best wishes
Dmitry
On Thu, Oct 09, 2025 at 07:42:37PM +0300, Dmitry Baryshkov wrote:
> On Thu, Oct 09, 2025 at 10:35:52AM +0200, Konrad Dybcio wrote:
> > On 10/8/25 9:08 PM, Dmitry Baryshkov wrote:
> > > On Wed, Oct 08, 2025 at 11:11:43AM +0200, Konrad Dybcio wrote:
> > >> On 10/8/25 10:00 AM, Konrad Dybcio wrote:
> > >>> On 10/8/25 6:41 AM, Krishna Chaitanya Chundru wrote:
> > >>>>
> > >>>>
> > >>>> On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
> > >>>>> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
> > >>>>>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
> > >>>>>> and x2 lane.
> > >>>>>>
> > >>>>>
> > >>>>> I tried to boot the upstream kernel (next-20250925 defconfig) on my
> > >>>>> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
> > >>>>> is crashing during boot as PCIe is being probed.
> > >>>>>
> > >>>>> Is this a known problem? Is there any workaround/changes in flight that
> > >>>>> I'm missing?
> > >>>>>
> > >>>> Hi Bjorn,
> > >>>>
> > >>>> we need this fix for the PCIe to work properly. Please try it once.
> > >>>> https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/
> > >>>
> > >>> This surely shouldn't cause/fix any issues, no?
> > >>
> > >> Apparently this is a real fix, because sm8750.dtsi defines the PCIe
> > >> PHY under a port node, while the MTP DT assigns perst-gpios to the RC
> > >> node, which the legacy binding ("everything under the RC node") parsing
> > >> code can't cope with (please mention that in the commit message, Krishna)
> > >>
> > >> And I couldn't come up with a way to describe "either both are required
> > >> if any is present under the RC node or none are allowed" in yaml
> > >
> > > What about:
> > >
> > > oneOf:
> > > - required:
> > > - foo
> > > - bar
> > > - properties:
> > > foo: false
> > > bar: false
> >
> > Oh yeah, this works.. would you mind submitting a patch like this, with a
>
> I'd prefer it it comes from somebody who is actually working on PCIe so
> that the explanations are not ridiculous. Mani?
>
Will do.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 10/2/25 1:37 AM, Bjorn Andersson wrote: > On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote: >> Add PCIe controller and PHY nodes which supports data rates of 8GT/s >> and x2 lane. >> > > I tried to boot the upstream kernel (next-20250925 defconfig) on my > Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device > is crashing during boot as PCIe is being probed. > > Is this a known problem? Is there any workaround/changes in flight that > I'm missing? Would enabling USB fix it? I think we went over it with some other IP block due to funny interconnect dependencies, but I'm surprised the series for USB is still not fully brought to completion.. Konrad
On 10/2/2025 5:07 AM, Bjorn Andersson wrote:
> On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote:
>> Add PCIe controller and PHY nodes which supports data rates of 8GT/s
>> and x2 lane.
>>
>
> I tried to boot the upstream kernel (next-20250925 defconfig) on my
> Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device
> is crashing during boot as PCIe is being probed.
>
> Is this a known problem? Is there any workaround/changes in flight that
> I'm missing?
>
The only required change for this is the driver change in this series
[3/3] PCI: qcom: Restrict port parsing only to pci child nodes
- Krishna Chaitanya.
> Regards,
> Bjorn
>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 180 ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 179 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index 4643705021c6ca095a16d8d7cc3adac920b21e82..b47668a64bcead3e48f58eeb2e41c04660493cb7 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -631,7 +631,7 @@ gcc: clock-controller@100000 {
>> clocks = <&bi_tcxo_div2>,
>> <0>,
>> <&sleep_clk>,
>> - <0>,
>> + <&pcie0_phy>,
>> <0>,
>> <0>,
>> <0>,
>> @@ -3304,6 +3304,184 @@ gic_its: msi-controller@16040000 {
>> };
>> };
>>
>> + pcie0: pcie@1c00000 {
>> + device_type = "pci";
>> + compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
>> + reg = <0x0 0x01c00000 0x0 0x3000>,
>> + <0x0 0x40000000 0x0 0xf1d>,
>> + <0x0 0x40000f20 0x0 0xa8>,
>> + <0x0 0x40001000 0x0 0x1000>,
>> + <0x0 0x40100000 0x0 0x100000>,
>> + <0x0 0x01C03000 0x0 0x1000>;
>> + reg-names = "parf",
>> + "dbi",
>> + "elbi",
>> + "atu",
>> + "config",
>> + "mhi";
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
>> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>,
>> + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>;
>> + bus-range = <0x00 0xff>;
>> +
>> + dma-coherent;
>> +
>> + linux,pci-domain = <0>;
>> +
>> + msi-map = <0x0 &gic_its 0x1400 0x1>,
>> + <0x100 &gic_its 0x1401 0x1>;
>> + msi-map-mask = <0xff00>;
>> +
>> + num-lanes = <2>;
>> +
>> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "msi0",
>> + "msi1",
>> + "msi2",
>> + "msi3",
>> + "msi4",
>> + "msi5",
>> + "msi6",
>> + "msi7",
>> + "global";
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
>> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
>> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
>> + clock-names = "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a",
>> + "ddrss_sf_tbu",
>> + "noc_aggr",
>> + "cnoc_sf_axi";
>> +
>> + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "pcie-mem",
>> + "cpu-pcie";
>> +
>> + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
>> + <0x100 &apps_smmu 0x1401 0x1>;
>> +
>> + resets = <&gcc GCC_PCIE_0_BCR>;
>> + reset-names = "pci";
>> +
>> + power-domains = <&gcc GCC_PCIE_0_GDSC>;
>> +
>> + operating-points-v2 = <&pcie0_opp_table>;
>> +
>> + status = "disabled";
>> +
>> + pcie0_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + /* GEN 1 x1 */
>> + opp-2500000 {
>> + opp-hz = /bits/ 64 <2500000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <250000 1>;
>> + };
>> +
>> + /* GEN 1 x2 and GEN 2 x1 */
>> + opp-5000000 {
>> + opp-hz = /bits/ 64 <5000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <500000 1>;
>> + };
>> +
>> + /* GEN 2 x2 */
>> + opp-10000000 {
>> + opp-hz = /bits/ 64 <10000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <1000000 1>;
>> + };
>> +
>> + /* GEN 3 x1 */
>> + opp-8000000 {
>> + opp-hz = /bits/ 64 <8000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <984500 1>;
>> + };
>> +
>> + /* GEN 3 x2 */
>> + opp-16000000 {
>> + opp-hz = /bits/ 64 <16000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <1969000 1>;
>> + };
>> +
>> + };
>> +
>> + pcieport0: pcie@0 {
>> + device_type = "pci";
>> + reg = <0x0 0x0 0x0 0x0 0x0>;
>> + bus-range = <0x01 0xff>;
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges;
>> + phys = <&pcie0_phy>;
>> + };
>> + };
>> +
>> + pcie0_phy: phy@1c06000 {
>> + compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
>> + reg = <0 0x01c06000 0 0x2000>;
>> +
>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
>> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
>> + <&gcc GCC_PCIE_0_PIPE_CLK>;
>> + clock-names = "aux",
>> + "cfg_ahb",
>> + "ref",
>> + "rchng",
>> + "pipe";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
>> + assigned-clock-rates = <100000000>;
>> +
>> + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>> + reset-names = "phy";
>> +
>> + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
>> +
>> + #clock-cells = <0>;
>> + clock-output-names = "pcie0_pipe_clk";
>> +
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> ufs_mem_phy: phy@1d80000 {
>> compatible = "qcom,sm8750-qmp-ufs-phy";
>> reg = <0x0 0x01d80000 0x0 0x2000>;
>>
>> --
>> 2.34.1
>>
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