The CSI-2 receiver in the i.MX8ULP is almost identical to the version
present in the i.MX8QXP/QM. They both include an optional Control and
Status Register (CSR) interface. The csr clock is the input clock for
its APB interface. For i.MXQXP/QM, the clock is always on when system
power up. For i.MX8ULP, the clock needs to be controlled by consumer.
For i.MX8MQ, it doesn't include CSR module. So add a device-specific
compatible string for i.MX8ULP to handle the difference.
Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
---
.../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 40 ++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
index 3389bab266a9adbda313c8ad795b998641df12f3..0bdd419a7ea12651bd514b6570fe208a99f0d6d9 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
@@ -21,7 +21,9 @@ properties:
- fsl,imx8mq-mipi-csi2
- fsl,imx8qxp-mipi-csi2
- items:
- - const: fsl,imx8qm-mipi-csi2
+ - enum:
+ - fsl,imx8qm-mipi-csi2
+ - fsl,imx8ulp-mipi-csi2
- const: fsl,imx8qxp-mipi-csi2
reg:
@@ -39,12 +41,16 @@ properties:
clock that the RX DPHY receives.
- description: ui is the pixel clock (phy_ref up to 333Mhz).
See the reference manual for details.
+ - description: csr is the APB pclk for CSR APB interface.
+ minItems: 3
clock-names:
items:
- const: core
- const: esc
- const: ui
+ - const: csr
+ minItems: 3
power-domains:
maxItems: 1
@@ -125,19 +131,49 @@ required:
- ports
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8ulp-mipi-csi2
+ then:
+ properties:
+ reg:
+ minItems: 2
+ resets:
+ minItems: 2
+ maxItems: 2
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-mipi-csi2
+ - fsl,imx8qm-mipi-csi2
+ not:
+ contains:
+ enum:
+ - fsl,imx8ulp-mipi-csi2
then:
properties:
reg:
minItems: 2
resets:
maxItems: 1
- else:
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mq-mipi-csi2
+ then:
properties:
reg:
maxItems: 1
--
2.34.1On Mon, Aug 25, 2025 at 06:10:10PM +0800, Guoniu Zhou wrote:
> The CSI-2 receiver in the i.MX8ULP is almost identical to the version
> present in the i.MX8QXP/QM. They both include an optional Control and
> Status Register (CSR) interface. The csr clock is the input clock for
> its APB interface. For i.MXQXP/QM, the clock is always on when system
^^^^
Do you means APB clock? you need specific it.
> power up. For i.MX8ULP, the clock needs to be controlled by consumer.
> For i.MX8MQ, it doesn't include CSR module.
About reason is enough, you can remove it.
> So add a device-specific
> compatible string for i.MX8ULP to handle the difference.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
> ---
> .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 40 ++++++++++++++++++++--
> 1 file changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> index 3389bab266a9adbda313c8ad795b998641df12f3..0bdd419a7ea12651bd514b6570fe208a99f0d6d9 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> @@ -21,7 +21,9 @@ properties:
> - fsl,imx8mq-mipi-csi2
> - fsl,imx8qxp-mipi-csi2
> - items:
> - - const: fsl,imx8qm-mipi-csi2
> + - enum:
> + - fsl,imx8qm-mipi-csi2
> + - fsl,imx8ulp-mipi-csi2
> - const: fsl,imx8qxp-mipi-csi2
>
> reg:
> @@ -39,12 +41,16 @@ properties:
> clock that the RX DPHY receives.
> - description: ui is the pixel clock (phy_ref up to 333Mhz).
> See the reference manual for details.
> + - description: csr is the APB pclk for CSR APB interface.
> + minItems: 3
>
> clock-names:
> items:
> - const: core
> - const: esc
> - const: ui
> + - const: csr
> + minItems: 3
You loss the restriction for fsl,imx8qm-mipi-csi2 and fsl,imx8qxp-mipi-csi2
previous is maxItems is 3, now become 4.
Opitons 1:
commit message: allow other platform at add apb clock, which normally
always on, but real reflact hardware clock's schema.
The key point is
You add new compatible string, which loss clocks and clocks-name restriction
for exised compatible string. Reviewer is not sure if it is what your
expected or just a mistake.
If you still have question, please ping me by team.
Frank
>
> power-domains:
> maxItems: 1
> @@ -125,19 +131,49 @@ required:
> - ports
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8ulp-mipi-csi2
> + then:
> + properties:
> + reg:
> + minItems: 2
> + resets:
> + minItems: 2
> + maxItems: 2
> + clocks:
> + minItems: 4
> + clock-names:
> + minItems: 4
> +
> - if:
> properties:
> compatible:
> contains:
> enum:
> - fsl,imx8qxp-mipi-csi2
> + - fsl,imx8qm-mipi-csi2
> + not:
> + contains:
> + enum:
> + - fsl,imx8ulp-mipi-csi2
> then:
> properties:
> reg:
> minItems: 2
> resets:
> maxItems: 1
options:
clocks:
maxItems: 3
clock-names:
maxItems: 3
> - else:
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8mq-mipi-csi2
> + then:
> properties:
> reg:
> maxItems: 1
>
> --
> 2.34.1
>
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