Describe JH7110 SoC DDR external memory interface.

Signed-off-by: E Shattow <e@freeshell.de>
---
 .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
new file mode 100644
index 000000000000..d65313b33a3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 DMC
+
+maintainers:
+  - E Shattow <e@freeshell.de>
+
+description:
+  JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
+  2133Mbps (up to 2800Mbps).
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-dmc
+
+  reg:
+    items:
+      - description: controller registers
+      - description: phy registers
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pll
+
+  resets:
+    items:
+      - description: axi
+      - description: osc
+      - description: apb
+
+  reset-names:
+    items:
+      - const: axi
+      - const: osc
+      - const: apb
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memory-controller@15700000 {
+        compatible = "starfive,jh7110-dmc";
+        reg = <0x0 0x15700000 0x0 0x10000>,
+              <0x0 0x13000000 0x0 0x10000>;
+        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+        clock-names = "pll";
+        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+                 <&syscrg JH7110_SYSRST_DDR_OSC>,
+                 <&syscrg JH7110_SYSRST_DDR_APB>;
+        reset-names = "axi", "osc", "apb";
+      };
+    };
-- 
2.50.0

On Sat, Aug 23, 2025 at 03:01:41AM -0700, E Shattow wrote:
> Describe JH7110 SoC DDR external memory interface.
> 
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>  .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

There is no memory controllers driver change, so I am fine if this goes
via SoC/DTS tree.  If you want me to pick it up, please ping on IRC.

Best regards,
Krzysztof

On Sun, Aug 24, 2025 at 11:25:08AM +0200, Krzysztof Kozlowski wrote:
> On Sat, Aug 23, 2025 at 03:01:41AM -0700, E Shattow wrote:
> > Describe JH7110 SoC DDR external memory interface.
> > 
> > Signed-off-by: E Shattow <e@freeshell.de>
> > ---
> >  .../starfive,jh7110-dmc.yaml                  | 74 +++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> There is no memory controllers driver change, so I am fine if this goes
> via SoC/DTS tree.  If you want me to pick it up, please ping on IRC.

That's cool, I will take it with the dts changes. Thanks.

On 8/23/25 08:20, Krzysztof Kozlowski wrote:
> On 23/08/2025 10:58, E Shattow wrote:
>> Describe JH7110 SoC DDR external memory interface.
>>
>> Signed-off-by: E Shattow <e@freeshell.de>
>
> Don't send the same patch multiple times. To which one people should
> respond?
>
> Best regards,
> Krzysztof

Respond to v3 RESEND (this thread), or I may collect responses from
either thread they are the same content. I'd missed a linux-riscv list
CC line on a patch and that confused patchwork, and then I missed
'RESEND' in subject for the re-send series after the cover letter.
Patchwork sees the RESEND series now, and sorry for the added noise. -E