[PATCH 0/8] riscv: add initial support for hardware breakpoints

Jesse Taube posted 8 patches 1 month, 1 week ago
arch/riscv/Kconfig                            |   2 +
arch/riscv/include/asm/bug.h                  |  12 -
arch/riscv/include/asm/hw_breakpoint.h        |  59 ++
arch/riscv/include/asm/insn.h                 | 132 ++-
arch/riscv/include/asm/kdebug.h               |   3 +-
arch/riscv/include/asm/processor.h            |   4 +
arch/riscv/include/asm/sbi.h                  |  33 +-
arch/riscv/include/uapi/asm/ptrace.h          |   9 +
arch/riscv/kernel/Makefile                    |   2 +
arch/riscv/kernel/hw_breakpoint.c             | 763 ++++++++++++++++++
arch/riscv/kernel/insn.c                      | 165 ++++
arch/riscv/kernel/kgdb.c                      | 102 +--
arch/riscv/kernel/probes/kprobes.c            |   1 +
arch/riscv/kernel/process.c                   |   4 +
arch/riscv/kernel/ptrace.c                    | 169 ++++
arch/riscv/kernel/traps.c                     |  11 +-
arch/riscv/kernel/traps_misaligned.c          |  93 +--
include/uapi/linux/elf.h                      |   2 +
tools/include/uapi/linux/elf.h                |   1 +
tools/perf/tests/tests.h                      |   3 +-
tools/testing/selftests/riscv/Makefile        |   2 +-
.../selftests/riscv/breakpoints/.gitignore    |   1 +
.../selftests/riscv/breakpoints/Makefile      |  13 +
.../riscv/breakpoints/breakpoint_test.c       | 246 ++++++
24 files changed, 1641 insertions(+), 191 deletions(-)
create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
create mode 100644 arch/riscv/kernel/hw_breakpoint.c
create mode 100644 arch/riscv/kernel/insn.c
create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore
create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile
create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c
[PATCH 0/8] riscv: add initial support for hardware breakpoints
Posted by Jesse Taube 1 month, 1 week ago
This patchset adds initial support for hardware breakpoints and
watchpoints to the  RISC-V architecture. The framework is built on
top of perf subsystem and SBI debug trigger extension.

Currently following features are not supported and are in works:
 - icount for single stepping
 - Virtualization of debug triggers
 - kernel space debug triggers

The SBI debug trigger extension can be found at:
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-debug-triggers.adoc

The Sdtrig ISA is part of RISC-V debug specification which can be
found at:
https://github.com/riscv/riscv-debug-spec

based off the original RFC by Himanshu Chauhan here:
https://lore.kernel.org/lkml/20240222125059.13331-1-hchauhan@ventanamicro.com/

Second RFC by Jesse Taube here:
https://lore.kernel.org/lkml/20250722173829.984082-1-jesse@rivosinc.com/

Himanshu Chauhan (2):
  riscv: Add SBI debug trigger extension and function ids
  riscv: Introduce support for hardware break/watchpoints

Jesse Taube (6):
  riscv: Add insn.c, consolidate instruction decoding
  riscv: insn: Add get_insn_nofault
  riscv: hw_breakpoint: Use icount for single stepping
  riscv: ptrace: Add hw breakpoint support
  riscv: ptrace: Add hw breakpoint regset
  selftests: riscv: Add test for hardware breakpoints

 arch/riscv/Kconfig                            |   2 +
 arch/riscv/include/asm/bug.h                  |  12 -
 arch/riscv/include/asm/hw_breakpoint.h        |  59 ++
 arch/riscv/include/asm/insn.h                 | 132 ++-
 arch/riscv/include/asm/kdebug.h               |   3 +-
 arch/riscv/include/asm/processor.h            |   4 +
 arch/riscv/include/asm/sbi.h                  |  33 +-
 arch/riscv/include/uapi/asm/ptrace.h          |   9 +
 arch/riscv/kernel/Makefile                    |   2 +
 arch/riscv/kernel/hw_breakpoint.c             | 763 ++++++++++++++++++
 arch/riscv/kernel/insn.c                      | 165 ++++
 arch/riscv/kernel/kgdb.c                      | 102 +--
 arch/riscv/kernel/probes/kprobes.c            |   1 +
 arch/riscv/kernel/process.c                   |   4 +
 arch/riscv/kernel/ptrace.c                    | 169 ++++
 arch/riscv/kernel/traps.c                     |  11 +-
 arch/riscv/kernel/traps_misaligned.c          |  93 +--
 include/uapi/linux/elf.h                      |   2 +
 tools/include/uapi/linux/elf.h                |   1 +
 tools/perf/tests/tests.h                      |   3 +-
 tools/testing/selftests/riscv/Makefile        |   2 +-
 .../selftests/riscv/breakpoints/.gitignore    |   1 +
 .../selftests/riscv/breakpoints/Makefile      |  13 +
 .../riscv/breakpoints/breakpoint_test.c       | 246 ++++++
 24 files changed, 1641 insertions(+), 191 deletions(-)
 create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
 create mode 100644 arch/riscv/kernel/hw_breakpoint.c
 create mode 100644 arch/riscv/kernel/insn.c
 create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore
 create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile
 create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c

-- 
2.43.0
Re: [PATCH 0/8] riscv: add initial support for hardware breakpoints
Posted by Jesse Taube 1 month, 1 week ago
On Fri, Aug 22, 2025 at 10:47 AM Jesse Taube <jesse@rivosinc.com> wrote:
>
> This patchset adds initial support for hardware breakpoints and
> watchpoints to the  RISC-V architecture. The framework is built on
> top of perf subsystem and SBI debug trigger extension.
>
> Currently following features are not supported and are in works:
>  - icount for single stepping
>  - Virtualization of debug triggers
>  - kernel space debug triggers
>
> The SBI debug trigger extension can be found at:
> https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-debug-triggers.adoc
>
> The Sdtrig ISA is part of RISC-V debug specification which can be
> found at:
> https://github.com/riscv/riscv-debug-spec
>
> based off the original RFC by Himanshu Chauhan here:
> https://lore.kernel.org/lkml/20240222125059.13331-1-hchauhan@ventanamicro.com/
>
> Second RFC by Jesse Taube here:
> https://lore.kernel.org/lkml/20250722173829.984082-1-jesse@rivosinc.com/
>
> Himanshu Chauhan (2):
>   riscv: Add SBI debug trigger extension and function ids
>   riscv: Introduce support for hardware break/watchpoints
>
> Jesse Taube (6):
>   riscv: Add insn.c, consolidate instruction decoding
>   riscv: insn: Add get_insn_nofault
>   riscv: hw_breakpoint: Use icount for single stepping
>   riscv: ptrace: Add hw breakpoint support
>   riscv: ptrace: Add hw breakpoint regset
>   selftests: riscv: Add test for hardware breakpoints
>
>  arch/riscv/Kconfig                            |   2 +
>  arch/riscv/include/asm/bug.h                  |  12 -
>  arch/riscv/include/asm/hw_breakpoint.h        |  59 ++
>  arch/riscv/include/asm/insn.h                 | 132 ++-
>  arch/riscv/include/asm/kdebug.h               |   3 +-
>  arch/riscv/include/asm/processor.h            |   4 +
>  arch/riscv/include/asm/sbi.h                  |  33 +-
>  arch/riscv/include/uapi/asm/ptrace.h          |   9 +
>  arch/riscv/kernel/Makefile                    |   2 +
>  arch/riscv/kernel/hw_breakpoint.c             | 763 ++++++++++++++++++
>  arch/riscv/kernel/insn.c                      | 165 ++++
>  arch/riscv/kernel/kgdb.c                      | 102 +--
>  arch/riscv/kernel/probes/kprobes.c            |   1 +
>  arch/riscv/kernel/process.c                   |   4 +
>  arch/riscv/kernel/ptrace.c                    | 169 ++++
>  arch/riscv/kernel/traps.c                     |  11 +-
>  arch/riscv/kernel/traps_misaligned.c          |  93 +--
>  include/uapi/linux/elf.h                      |   2 +
>  tools/include/uapi/linux/elf.h                |   1 +
>  tools/perf/tests/tests.h                      |   3 +-
>  tools/testing/selftests/riscv/Makefile        |   2 +-
>  .../selftests/riscv/breakpoints/.gitignore    |   1 +
>  .../selftests/riscv/breakpoints/Makefile      |  13 +
>  .../riscv/breakpoints/breakpoint_test.c       | 246 ++++++
>  24 files changed, 1641 insertions(+), 191 deletions(-)
>  create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
>  create mode 100644 arch/riscv/kernel/hw_breakpoint.c
>  create mode 100644 arch/riscv/kernel/insn.c
>  create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore
>  create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile
>  create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c
>
> --
> 2.43.0
>

Oops, this meant to be V2.

Thanks,
Jesse Taube