The msleep(10) in dpc_wait_rp_inactive() may sleep longer than intended
due to timer granularity, which can cause unnecessary delays in downstream
port containment recovery. Replace it with usleep_range() for a more
precise delay of approximately 10ms.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/pcie/dpc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
index fc18349614d7..ff0884d669b7 100644
--- a/drivers/pci/pcie/dpc.c
+++ b/drivers/pci/pcie/dpc.c
@@ -21,6 +21,8 @@
#define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL | \
PCI_EXP_DPC_CTL_EN_NONFATAL)
+#define PCIE_EXP_DPC_BUSY_CHECK_US 10000
+
static const char * const rp_pio_error_string[] = {
"Configuration Request received UR Completion", /* Bit Position 0 */
"Configuration Request received CA Completion", /* Bit Position 1 */
@@ -135,7 +137,8 @@ static int dpc_wait_rp_inactive(struct pci_dev *pdev)
pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
while (status & PCI_EXP_DPC_RP_BUSY &&
!time_after(jiffies, timeout)) {
- msleep(10);
+ usleep_range(PCIE_EXP_DPC_BUSY_CHECK_US,
+ PCIE_EXP_DPC_BUSY_CHECK_US + 100);
pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
}
if (status & PCI_EXP_DPC_RP_BUSY) {
--
2.25.1