Hi James,
On 8/22/25 16:30, James Morse wrote:
> From: Rohit Mathew <rohit.mathew@arm.com>
>
> If the 44 bit (long) or 63 bit (LWD) counters are detected on probing
> the RIS, use long/LWD counter instead of the regular 31 bit mbwu
> counter.
>
> Only 32bit accesses to the MSC are required to be supported by the
> spec, but these registers are 64bits. The lower half may overflow
> into the higher half between two 32bit reads. To avoid this, use
> a helper that reads the top half multiple times to check for overflow.
>
> Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
> [morse: merged multiple patches from Rohit]
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> Changes since RFC:
> * Commit message wrangling.
> * Refer to 31 bit counters as opposed to 32 bit (registers).
> ---
> drivers/resctrl/mpam_devices.c | 89 ++++++++++++++++++++++++++++++----
> 1 file changed, 80 insertions(+), 9 deletions(-)
>
Looks good to me.
Reviewed-by: Ben Horgan <ben.horgan@arm.com>
> diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
> index 2ab7f127baaa..8fbcf6eb946a 100644
> --- a/drivers/resctrl/mpam_devices.c
> +++ b/drivers/resctrl/mpam_devices.c
> @@ -1002,6 +1002,48 @@ struct mon_read {
> int err;
> };
>
> +static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris)
> +{
> + return (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, &ris->props) ||
> + mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props));
> +}
> +
> +static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
> +{
> + int retry = 3;
> + u32 mbwu_l_low;
> + u64 mbwu_l_high1, mbwu_l_high2;
> +
> + mpam_mon_sel_lock_held(msc);
> +
> + WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
> + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
> +
> + mbwu_l_high2 = __mpam_read_reg(msc, MSMON_MBWU_L + 4);
> + do {
> + mbwu_l_high1 = mbwu_l_high2;
> + mbwu_l_low = __mpam_read_reg(msc, MSMON_MBWU_L);
> + mbwu_l_high2 = __mpam_read_reg(msc, MSMON_MBWU_L + 4);
> +
> + retry--;
> + } while (mbwu_l_high1 != mbwu_l_high2 && retry > 0);
> +
> + if (mbwu_l_high1 == mbwu_l_high2)
> + return (mbwu_l_high1 << 32) | mbwu_l_low;
> + return MSMON___NRDY_L;
> +}
> +
> +static void mpam_msc_zero_mbwu_l(struct mpam_msc *msc)
> +{
> + mpam_mon_sel_lock_held(msc);
> +
> + WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
> + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
> +
> + __mpam_write_reg(msc, MSMON_MBWU_L, 0);
> + __mpam_write_reg(msc, MSMON_MBWU_L + 4, 0);
> +}
> +
> static void gen_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
> u32 *flt_val)
> {
> @@ -1058,6 +1100,7 @@ static void read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
> static void clean_msmon_ctl_val(u32 *cur_ctl)
> {
> *cur_ctl &= ~MSMON_CFG_x_CTL_OFLOW_STATUS;
> + *cur_ctl &= ~MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L;
I observe that this bit is res0, in the CSU case, and so the clearing is ok.
> }
>
> static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val,
> @@ -1080,7 +1123,11 @@ static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val,
> case mpam_feat_msmon_mbwu:
> mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val);
> mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val);
> - mpam_write_monsel_reg(msc, MBWU, 0);
> + if (mpam_ris_has_mbwu_long_counter(m->ris))
> + mpam_msc_zero_mbwu_l(m->ris->vmsc->msc);
> + else
> + mpam_write_monsel_reg(msc, MBWU, 0);
> +
> mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val | MSMON_CFG_x_CTL_EN);
>
> mbwu_state = &m->ris->mbwu_state[m->ctx->mon];
> @@ -1095,8 +1142,13 @@ static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val,
>
> static u64 mpam_msmon_overflow_val(struct mpam_msc_ris *ris)
> {
> - /* TODO: scaling, and long counters */
> - return GENMASK_ULL(30, 0);
> + /* TODO: implement scaling counters */
> + if (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, &ris->props))
> + return GENMASK_ULL(62, 0);
> + else if (mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props))
> + return GENMASK_ULL(43, 0);
> + else
> + return GENMASK_ULL(30, 0);
> }
>
> /* Call with MSC lock held */
> @@ -1138,10 +1190,24 @@ static void __ris_msmon_read(void *arg)
> now = FIELD_GET(MSMON___VALUE, now);
> break;
> case mpam_feat_msmon_mbwu:
> - now = mpam_read_monsel_reg(msc, MBWU);
> - if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops))
> - nrdy = now & MSMON___NRDY;
> - now = FIELD_GET(MSMON___VALUE, now);
> + /*
> + * If long or lwd counters are supported, use them, else revert
> + * to the 31 bit counter.
> + */
> + if (mpam_ris_has_mbwu_long_counter(ris)) {
> + now = mpam_msc_read_mbwu_l(msc);
> + if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops))
> + nrdy = now & MSMON___NRDY_L;
> + if (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, rprops))
> + now = FIELD_GET(MSMON___LWD_VALUE, now);
> + else
> + now = FIELD_GET(MSMON___L_VALUE, now);
> + } else {
> + now = mpam_read_monsel_reg(msc, MBWU);
> + if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops))
> + nrdy = now & MSMON___NRDY;
> + now = FIELD_GET(MSMON___VALUE, now);
> + }
>
> if (nrdy)
> break;
> @@ -1433,8 +1499,13 @@ static int mpam_save_mbwu_state(void *arg)
> cur_ctl = mpam_read_monsel_reg(msc, CFG_MBWU_CTL);
> mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0);
>
> - val = mpam_read_monsel_reg(msc, MBWU);
> - mpam_write_monsel_reg(msc, MBWU, 0);
> + if (mpam_ris_has_mbwu_long_counter(ris)) {
> + val = mpam_msc_read_mbwu_l(msc);
> + mpam_msc_zero_mbwu_l(msc);
> + } else {
> + val = mpam_read_monsel_reg(msc, MBWU);
> + mpam_write_monsel_reg(msc, MBWU, 0);
> + }
>
> cfg->mon = i;
> cfg->pmg = FIELD_GET(MSMON_CFG_MBWU_FLT_PMG, cur_flt);
--
Thanks,
Ben