The MTK VCP mailbox enables the SoC to communicate with the VCP by passing
messages through 64 32-bit wide registers. It has 32 interrupt vectors in
either direction for signalling purposes.
This adds a binding for Mediatek VCP mailbox.
Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com>
---
.../mailbox/mediatek,mt8196-vcp-mbox.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml
diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml
new file mode 100644
index 000000000000..7b1c5165e64e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Video Companion Processor (VCP) mailbox
+
+maintainers:
+ - Jjian Zhou <Jjian.Zhou@mediatek.com>
+
+description:
+ The MTK VCP mailbox enables the SoC to communicate with the VCP by passing
+ messages through 64 32-bit wide registers. It has 32 interrupt vectors in
+ either direction for signalling purposes.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8196-vcp-mbox
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#mbox-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ mailbox@31b80000 {
+ compatible = "mediatek,mt8196-vcp-mbox";
+ reg = <0x31b80000 0x1000>;
+ interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <0>;
+ };
--
2.46.0
On Fri, Aug 22, 2025 at 10:12:08AM +0800, Jjian Zhou wrote: > The MTK VCP mailbox enables the SoC to communicate with the VCP by passing > messages through 64 32-bit wide registers. It has 32 interrupt vectors in > either direction for signalling purposes. > > This adds a binding for Mediatek VCP mailbox. > > Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com> > --- > .../mailbox/mediatek,mt8196-vcp-mbox.yaml | 49 +++++++++++++++++++ > 1 file changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Aug 22, 2025 at 10:12 AM Jjian Zhou <jjian.zhou@mediatek.com> wrote: > > The MTK VCP mailbox enables the SoC to communicate with the VCP by passing > messages through 64 32-bit wide registers. It has 32 interrupt vectors in > either direction for signalling purposes. > > This adds a binding for Mediatek VCP mailbox. > > Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- > .../mailbox/mediatek,mt8196-vcp-mbox.yaml | 49 +++++++++++++++++++ > 1 file changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml > new file mode 100644 > index 000000000000..7b1c5165e64e > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml > @@ -0,0 +1,49 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Video Companion Processor (VCP) mailbox > + > +maintainers: > + - Jjian Zhou <Jjian.Zhou@mediatek.com> > + > +description: > + The MTK VCP mailbox enables the SoC to communicate with the VCP by passing > + messages through 64 32-bit wide registers. It has 32 interrupt vectors in > + either direction for signalling purposes. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8196-vcp-mbox > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + "#mbox-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - interrupts > + - "#mbox-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + mailbox@31b80000 { > + compatible = "mediatek,mt8196-vcp-mbox"; > + reg = <0x31b80000 0x1000>; > + interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH 0>; > + #mbox-cells = <0>; > + }; > -- > 2.46.0 >
© 2016 - 2025 Red Hat, Inc.