From: Ziyao <liziyao@uniontech.com>

Older steppings of the Loongson 3C6000 series incorrectly report the
supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as
only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s
up to 16 GT/s.

As a result, certain PCIe devices would be incorrectly probed as a Gen1-
only, even if higher link speeds are supported, harming performance and
prevents dynamic link speed functionality from being enabled in drivers
such as amdgpu.

Manually override the `supported_speeds` field for affected PCIe bridges
with those found on the upstream bus to correctly reflect the supported
link speeds.

This patch is found from AOSC OS[1].

Link: https://github.com/AOSC-Tracking/linux/pull/2 #1
Tested-by: Lain Fearyncess Yang <fsf@live.com>
Tested-by: Mingcong Bai <jeffbai@aosc.io>
Tested-by: Ayden Meng <aydenmeng@yeah.net>
Signed-off-by: Ayden Meng <aydenmeng@yeah.net>
Signed-off-by: Ziyao <liziyao@uniontech.com>
---
PCI: Override PCIe bridge supported speeds for older Loongson 3C6000
 series steppings
---
 drivers/pci/quirks.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index d97335a401930fe8204e7ca91a8474b6b02554c1..8d29b130f45854d2bff8c47e6529a41a3231221e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1956,6 +1956,30 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7525_MCH,	quir
 
 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
 
+/*
+ * Older steppings of the Loongson 3C6000 series incorrectly report the
+ * supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as
+ * only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s
+ * up to 16 GT/s.
+ */
+static void quirk_loongson_pci_bridge_supported_speeds(struct pci_dev *pdev)
+{
+	switch (pdev->bus->max_bus_speed) {
+	case PCIE_SPEED_16_0GT:
+		pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB;
+	case PCIE_SPEED_8_0GT:
+		pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB;
+	case PCIE_SPEED_5_0GT:
+		pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;
+	case PCIE_SPEED_2_5GT:
+		pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB;
+	default:
+		break;
+	}
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, quirk_loongson_secondary_bridge_supported_speeds);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, quirk_loongson_secondary_bridge_supported_speeds);
+
 /*
  * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
  * actually on the AMBA bus. These fake PCI devices can support SVA via

---
base-commit: 3957a5720157264dcc41415fbec7c51c4000fc2d
change-id: 20250822-loongson-pci1-4ded0d78f1bb

Best regards,
-- 
Ziyao <liziyao@uniontech.com>

On Fri, Aug 22, 2025 at 05:15:58PM +0800, Ziyao via B4 Relay wrote:
> Older steppings of the Loongson 3C6000 series incorrectly report the
> supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as
> only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s
> up to 16 GT/s.

I assume these bridges (Root Ports?) are only found on LS3C6000 CPUs?

If so, please put the quirk in arch/loongarch/pci/pci.c or
drivers/pci/controller/pci-loongson.c alongside the existing fixups there.

drivers/pci/quirks.c is compiled on all arches and if these bridges
only exist on certain Loongson CPUs, the quirk isn't needed on other
arches and wastes memory.

Also, please consider adding entries for 3c19, 3c29 to the PCI IDs
database:

https://admin.pci-ids.ucw.cz/read/PC/0014

Thanks,

Lukas

Hi Ziyao,

kernel test robot noticed the following build errors:

[auto build test ERROR on 3957a5720157264dcc41415fbec7c51c4000fc2d]

url:    https://github.com/intel-lab-lkp/linux/commits/Ziyao-via-B4-Relay/PCI-Override-PCIe-bridge-supported-speeds-for-older-Loongson-3C6000-series-steppings/20250822-171721
base:   3957a5720157264dcc41415fbec7c51c4000fc2d
patch link:    https://lore.kernel.org/r/20250822-loongson-pci1-v1-1-39aabbd11fbd%40uniontech.com
patch subject: [PATCH RESEND] PCI: Override PCIe bridge supported speeds for older Loongson 3C6000 series steppings
config: alpha-allnoconfig (https://download.01.org/0day-ci/archive/20250823/202508230402.VUq5Fewo-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250823/202508230402.VUq5Fewo-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508230402.VUq5Fewo-lkp@intel.com/

All error/warnings (new ones prefixed by >>):

   In file included from drivers/pci/quirks.c:21:
>> drivers/pci/quirks.c:1980:58: error: 'quirk_loongson_secondary_bridge_supported_speeds' undeclared here (not in a function); did you mean 'quirk_loongson_pci_bridge_supported_speeds'?
    1980 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, quirk_loongson_secondary_bridge_supported_speeds);
         |                                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   include/linux/pci.h:2318:57: note: in definition of macro 'DECLARE_PCI_FIXUP_SECTION'
    2318 |                 = { vendor, device, class, class_shift, hook };
         |                                                         ^~~~
   drivers/pci/quirks.c:1980:1: note: in expansion of macro 'DECLARE_PCI_FIXUP_HEADER'
    1980 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, quirk_loongson_secondary_bridge_supported_speeds);
         | ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/quirks.c:1965:13: warning: 'quirk_loongson_pci_bridge_supported_speeds' defined but not used [-Wunused-function]
    1965 | static void quirk_loongson_pci_bridge_supported_speeds(struct pci_dev *pdev)
         |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +1980 drivers/pci/quirks.c

  1958	
  1959	/*
  1960	 * Older steppings of the Loongson 3C6000 series incorrectly report the
  1961	 * supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as
  1962	 * only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s
  1963	 * up to 16 GT/s.
  1964	 */
> 1965	static void quirk_loongson_pci_bridge_supported_speeds(struct pci_dev *pdev)
  1966	{
  1967		switch (pdev->bus->max_bus_speed) {
  1968		case PCIE_SPEED_16_0GT:
  1969			pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB;
  1970		case PCIE_SPEED_8_0GT:
  1971			pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB;
  1972		case PCIE_SPEED_5_0GT:
  1973			pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;
  1974		case PCIE_SPEED_2_5GT:
  1975			pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB;
  1976		default:
  1977			break;
  1978		}
  1979	}
> 1980	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, quirk_loongson_secondary_bridge_supported_speeds);
  1981	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, quirk_loongson_secondary_bridge_supported_speeds);
  1982	

-- 
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https://github.com/intel/lkp-tests/wiki