Add the LTDC node for stm32mp255 SoC and handle its loopback clocks.
ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is
semantically correct, it for now leads to an improper setting of the
clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does
not support changing rates yet. To overcome this issue, a fixed clock
can be used for the kernel clock.
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++
arch/arm64/boot/dts/st/stm32mp255.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 372a99d9cc5c3730e8fbeddeb6134a3b18d938b6..b44ff221e0da968be104ff8195f9bef79c90c57a 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec {
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
+
+ clk_flexgen_27_fixed: clk-54000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <54000000>;
+ };
};
firmware {
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index f689b47c5010033120146cf1954d6624c0270045..48a95af1741c42300195b753b710e714abc60d96 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -5,6 +5,12 @@
*/
#include "stm32mp253.dtsi"
+<dc {
+ compatible = "st,stm32mp255-ltdc";
+ clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>;
+ clock-names = "lcd", "bus", "ref", "lvds";
+};
+
&rifsc {
vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
--
2.25.1