The CSI-2 receiver in the i.MX8ULP is almost identical to the version
present in the i.MX8QXP/QM. But have different reset and clock design,
so add a device-specific compatible string for i.MX8ULP to handle the
difference.
Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
---
.../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 42 ++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
index 3389bab266a9adbda313c8ad795b998641df12f3..ca485d1d596c274eb7e1f3cdc39c61bb54cc0685 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
@@ -21,7 +21,9 @@ properties:
- fsl,imx8mq-mipi-csi2
- fsl,imx8qxp-mipi-csi2
- items:
- - const: fsl,imx8qm-mipi-csi2
+ - enum:
+ - fsl,imx8ulp-mipi-csi2
+ - fsl,imx8qm-mipi-csi2
- const: fsl,imx8qxp-mipi-csi2
reg:
@@ -39,12 +41,19 @@ properties:
clock that the RX DPHY receives.
- description: ui is the pixel clock (phy_ref up to 333Mhz).
See the reference manual for details.
+ - description: pclk is the lpav bus clock of i.MX8ULP. It provides
+ clock to CSI_REG module.
+ (see section "4.5.4 Peripheral clock diagrams,
+ Figure 76 MIPI CSI clocking" in IMX8ULPRM REV1)
+ minItems: 3
clock-names:
items:
- const: core
- const: esc
- const: ui
+ - const: pclk
+ minItems: 3
power-domains:
maxItems: 1
@@ -125,19 +134,48 @@ required:
- ports
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8ulp-mipi-csi2
+ then:
+ properties:
+ reg:
+ minItems: 2
+ resets:
+ maxItems: 2
+ minItems: 2
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-mipi-csi2
+ not:
+ contains:
+ enum:
+ - fsl,imx8ulp-mipi-csi2
then:
properties:
reg:
minItems: 2
resets:
maxItems: 1
- else:
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mq-mipi-csi2
+ then:
properties:
reg:
maxItems: 1
--
2.34.1
On Fri, Aug 22, 2025 at 06:50:12PM +0800, Guoniu Zhou wrote: > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > present in the i.MX8QXP/QM. But have different reset and clock design, > so add a device-specific compatible string for i.MX8ULP to handle the > difference. > > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> > --- > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 42 ++++++++++++++++++++-- > 1 file changed, 40 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > index 3389bab266a9adbda313c8ad795b998641df12f3..ca485d1d596c274eb7e1f3cdc39c61bb54cc0685 100644 > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > @@ -21,7 +21,9 @@ properties: > - fsl,imx8mq-mipi-csi2 > - fsl,imx8qxp-mipi-csi2 > - items: > - - const: fsl,imx8qm-mipi-csi2 > + - enum: > + - fsl,imx8ulp-mipi-csi2 > + - fsl,imx8qm-mipi-csi2 > - const: fsl,imx8qxp-mipi-csi2 > > reg: > @@ -39,12 +41,19 @@ properties: > clock that the RX DPHY receives. > - description: ui is the pixel clock (phy_ref up to 333Mhz). > See the reference manual for details. > + - description: pclk is the lpav bus clock of i.MX8ULP. It provides > + clock to CSI_REG module. > + (see section "4.5.4 Peripheral clock diagrams, > + Figure 76 MIPI CSI clocking" in IMX8ULPRM REV1) > + minItems: 3 > > clock-names: > items: > - const: core > - const: esc > - const: ui > + - const: pclk > + minItems: 3 > > power-domains: > maxItems: 1 > @@ -125,19 +134,48 @@ required: > - ports > > allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8ulp-mipi-csi2 > + then: > + properties: > + reg: > + minItems: 2 > + resets: > + maxItems: 2 > + minItems: 2 > + clocks: > + minItems: 4 > + clock-names: > + minItems: 4 > + Add else properties: clocks: - maxItems: 3 clock-names - maxItems: 3 to keep the same restriction for other compatible string Frank > - if: > properties: > compatible: > contains: > enum: > - fsl,imx8qxp-mipi-csi2 > + not: > + contains: > + enum: > + - fsl,imx8ulp-mipi-csi2 > then: > properties: > reg: > minItems: 2 > resets: > maxItems: 1 > - else: > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8mq-mipi-csi2 > + then: > properties: > reg: > maxItems: 1 > > -- > 2.34.1 >
On 22/08/2025 12:50, Guoniu Zhou wrote: > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > present in the i.MX8QXP/QM. But have different reset and clock design, > so add a device-specific compatible string for i.MX8ULP to handle the > difference. > > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> > --- > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 42 ++++++++++++++++++++-- > 1 file changed, 40 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > index 3389bab266a9adbda313c8ad795b998641df12f3..ca485d1d596c274eb7e1f3cdc39c61bb54cc0685 100644 > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > @@ -21,7 +21,9 @@ properties: > - fsl,imx8mq-mipi-csi2 > - fsl,imx8qxp-mipi-csi2 > - items: > - - const: fsl,imx8qm-mipi-csi2 > + - enum: > + - fsl,imx8ulp-mipi-csi2 > + - fsl,imx8qm-mipi-csi2 That;s some sort of random change. Previously code was correctly sorted - u > q... now it is not > - const: fsl,imx8qxp-mipi-csi2 > > reg: > @@ -39,12 +41,19 @@ properties: > clock that the RX DPHY receives. > - description: ui is the pixel clock (phy_ref up to 333Mhz). > See the reference manual for details. > + - description: pclk is the lpav bus clock of i.MX8ULP. It provides > + clock to CSI_REG module. > + (see section "4.5.4 Peripheral clock diagrams, > + Figure 76 MIPI CSI clocking" in IMX8ULPRM REV1) > + minItems: 3 > > clock-names: > items: > - const: core > - const: esc > - const: ui > + - const: pclk > + minItems: 3 > > power-domains: > maxItems: 1 > @@ -125,19 +134,48 @@ required: > - ports > > allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8ulp-mipi-csi2 > + then: > + properties: > + reg: > + minItems: 2 > + resets: > + maxItems: 2 > + minItems: 2 minItems goes before max. > + clocks: > + minItems: 4 > + clock-names: > + minItems: 4 > + > - if: > properties: > compatible: > contains: > enum: > - fsl,imx8qxp-mipi-csi2 > + not: > + contains: > + enum: > + - fsl,imx8ulp-mipi-csi2 > then: > properties: > reg: > minItems: 2 > resets: > maxItems: 1 > - else: > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8mq-mipi-csi2 > + then: > properties: > reg: > maxItems: 1 I don't see what we asked you for - restrict other variants. Answer previous review: "Or explain why old hardware has now 4 clocks. That explanation is missing." > Best regards, Krzysztof
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