Add required change in phy driver to support combo SS phy for this SoC.
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 325 +++++++++++++++++++-
include/linux/soc/samsung/exynos-regs-pmu.h | 1 +
2 files changed, 322 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 32178c5c120d..e0e90f614121 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -273,6 +273,36 @@
#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110
#define HSPPLLTUNE_FSEL GENMASK(18, 16)
+/* ExynosAutov920 phy usb31drd port reg */
+#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000
+#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5)
+#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4)
+#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1)
+#define PHY_RST_CTRL_PHY_RESET BIT(0)
+
+#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004
+#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16)
+#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8)
+#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4)
+#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0)
+
+#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008
+
+#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c
+#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0)
+#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16)
+
+#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100
+#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14)
+#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13)
+#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1)
+
+#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c
+#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24)
+
+#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110
+#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2)
+
/* Exynos9 - GS101 */
#define EXYNOS850_DRD_SECPMACTL 0x48
#define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12)
@@ -2077,6 +2107,251 @@ static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = {
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
};
+static void
+exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool high)
+{
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ u32 reg;
+
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+ if (high)
+ reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
+ else
+ reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
+
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+ fsleep(1);
+}
+
+static void
+exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd)
+{
+ struct device *dev = phy_drd->dev;
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ static const unsigned int timeout_us = 20000;
+ static const unsigned int sleep_us = 40;
+ u32 reg;
+ int err;
+
+ /* Clear cr_para_con */
+ reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
+ PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR);
+ reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+ writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1);
+ writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
+
+ exynosautov920_usb31drd_cr_clk(phy_drd, true);
+ exynosautov920_usb31drd_cr_clk(phy_drd, false);
+
+ /*
+ * The maximum time from phy reset de-assertion to de-assertion of
+ * tx/rx_ack can be as high as 5ms in fast simulation mode.
+ * Time to phy ready is < 20ms
+ */
+ err = readl_poll_timeout(reg_phy +
+ EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0,
+ reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK),
+ sleep_us, timeout_us);
+ if (err)
+ dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg);
+
+ reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+}
+
+static void
+exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd,
+ u16 addr, u16 data)
+{
+ struct device *dev = phy_drd->dev;
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ u32 cnt = 0;
+ u32 reg;
+
+ /* Pre Clocking */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+ reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+
+ /*
+ * tx clks must be available prior to assertion of tx req.
+ * tx pstate p2 to p0 transition directly is not permitted.
+ * tx clk ready must be asserted synchronously on tx clk prior
+ * to internal transmit clk alignment sequence in the phy
+ * when entering from p2 to p1 to p0.
+ */
+ do {
+ exynosautov920_usb31drd_cr_clk(phy_drd, true);
+ exynosautov920_usb31drd_cr_clk(phy_drd, false);
+ cnt++;
+ } while (cnt < 15);
+
+ reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+
+ /*
+ * tx data path is active when tx lane is in p0 state
+ * and tx data en asserted. enable cr_para_wr_en.
+ */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
+ reg &= ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA;
+ reg |= FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) |
+ PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
+
+ /* write addr */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+ reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR;
+ reg |= FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) |
+ PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
+ PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+
+ /* check cr_para_ack*/
+ cnt = 0;
+ do {
+ /*
+ * data symbols are captured by phy on rising edge of the
+ * tx_clk when tx data enabled.
+ * completion of the write cycle is acknowledged by assertion
+ * of the cr_para_ack.
+ */
+ exynosautov920_usb31drd_cr_clk(phy_drd, true);
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
+ if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK))
+ break;
+
+ exynosautov920_usb31drd_cr_clk(phy_drd, false);
+
+ /*
+ * wait for minimum of 10 cr_para_clk cycles after phy reset
+ * is negated, before accessing control regs to allow for
+ * internal resets.
+ */
+ cnt++;
+ } while (cnt < 10);
+
+ if (cnt < 10)
+ exynosautov920_usb31drd_cr_clk(phy_drd, false);
+}
+
+static void
+exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int val)
+{
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ u32 reg;
+
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+ reg &= ~PHY_RST_CTRL_PHY_RESET_OVRD_EN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+ if (val)
+ reg |= PHY_RST_CTRL_PHY_RESET;
+ else
+ reg &= ~PHY_RST_CTRL_PHY_RESET;
+
+ reg |= PHY_RST_CTRL_PHY_RESET_OVRD_EN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+}
+
+static void
+exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, int val)
+{
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ u32 reg;
+
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+ reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+ if (val)
+ reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N;
+ else
+ reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N;
+
+ reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
+}
+
+static void
+exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
+{
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ u32 reg;
+
+ /*
+ * Phy and Pipe Lane reset assert.
+ * assert reset (phy_reset = 1).
+ * The lane-ack outputs are asserted during reset (tx_ack = rx_ack = 1)
+ */
+ exynosautov920_usb31drd_phy_reset(phy_drd, 1);
+ exynosautov920_usb31drd_lane0_reset(phy_drd, 1);
+
+ /*
+ * ANA Power En, PCS & PMA PWR Stable Set
+ * ramp-up power suppiles
+ */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0);
+ reg |= PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE |
+ PHY_CONFIG0_PHY0_PMA_PWR_STABLE;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0);
+
+ fsleep(10);
+
+ /*
+ * phy is not functional in test_powerdown mode, test_powerdown to be
+ * de-asserted for normal operation
+ */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
+ reg &= ~PHY_CONFIG7_PHY_TEST_POWERDOWN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
+
+ /*
+ * phy reset signal be asserted for minimum 10us after power
+ * supplies are ramped-up
+ */
+ fsleep(10);
+
+ /*
+ * Phy and Pipe Lane reset assert de-assert
+ */
+ exynosautov920_usb31drd_phy_reset(phy_drd, 0);
+ exynosautov920_usb31drd_lane0_reset(phy_drd, 0);
+
+ /* Pipe_rx0_sris_mode_en = 1 */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4);
+ reg |= PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4);
+
+ /*
+ * wait for lane ack outputs to de-assert (tx_ack = rx_ack = 0)
+ * Exit from the reset state is indicated by de-assertion of *_ack
+ */
+ exynosautov920_usb31drd_port_phy_ready(phy_drd);
+
+ /* override values for level settings */
+ exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5);
+}
+
+static void
+exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd)
+{
+ void __iomem *reg_phy = phy_drd->reg_phy;
+ u32 reg;
+
+ /* 1. Assert reset (phy_reset = 1) */
+ exynosautov920_usb31drd_lane0_reset(phy_drd, 1);
+ exynosautov920_usb31drd_phy_reset(phy_drd, 1);
+
+ /* phy test power down */
+ reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
+ reg |= PHY_CONFIG7_PHY_TEST_POWERDOWN;
+ writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
+}
+
static void
exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
{
@@ -2172,12 +2447,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
/* after POR low and delay 75us, PHYCLOCK is guaranteed. */
fsleep(75);
- /* force pipe3 signal for link */
+ /* Disable forcing pipe interface */
reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL);
- reg |= LINKCTRL_FORCE_PIPE_EN;
- reg &= ~LINKCTRL_FORCE_PHYSTATUS;
- reg |= LINKCTRL_FORCE_RXELECIDLE;
+ reg &= ~LINKCTRL_FORCE_PIPE_EN;
writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
+
+ /* Pclk to pipe_clk */
+ reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST);
+ reg |= EXYNOS2200_CLKRST_LINK_PCLK_SEL;
+ writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
}
static void
@@ -2264,6 +2542,8 @@ static int exynosautov920_usbdrd_combo_phy_exit(struct phy *phy)
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
exynosautov920_usbdrd_hsphy_disable(phy_drd);
+ else if (inst->phy_cfg->id == EXYNOS5_DRDPHY_PIPE3)
+ exynosautov920_usb31drd_ssphy_disable(phy_drd);
/* enable PHY isol */
inst->phy_cfg->phy_isol(inst, true);
@@ -2320,10 +2600,44 @@ static int exynosautov920_usbdrd_phy_power_off(struct phy *phy)
return 0;
}
+static const char * const exynosautov920_usb30_regulators[] = {
+ "dvdd075-usb30", "vdd18-usb30",
+};
+
static const char * const exynosautov920_usb20_regulators[] = {
"dvdd075-usb20", "vdd18-usb20", "vdd33-usb20",
};
+static const struct
+exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] = {
+ {
+ .id = EXYNOS5_DRDPHY_PIPE3,
+ .phy_isol = exynos5_usbdrd_phy_isol,
+ .phy_init = exynosautov920_usb31drd_pipe3_init,
+ },
+};
+
+static const struct phy_ops exynosautov920_usb31drd_combo_ssphy_ops = {
+ .init = exynosautov920_usbdrd_phy_init,
+ .exit = exynosautov920_usbdrd_combo_phy_exit,
+ .power_on = exynosautov920_usbdrd_phy_power_on,
+ .power_off = exynosautov920_usbdrd_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static const
+struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_combo_ssphy = {
+ .phy_cfg = usb31drd_phy_cfg_exynosautov920,
+ .phy_ops = &exynosautov920_usb31drd_combo_ssphy_ops,
+ .pmu_offset_usbdrd0_phy = EXYNOSAUTOV920_PHY_CTRL_USB31,
+ .clk_names = exynos5_clk_names,
+ .n_clks = ARRAY_SIZE(exynos5_clk_names),
+ .core_clk_names = exynos5_core_clk_names,
+ .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
+ .regulator_names = exynosautov920_usb30_regulators,
+ .n_regulators = ARRAY_SIZE(exynosautov920_usb30_regulators),
+};
+
static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops = {
.init = exynosautov920_usbdrd_phy_init,
.exit = exynosautov920_usbdrd_combo_phy_exit,
@@ -2588,6 +2902,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
}, {
.compatible = "samsung,exynos990-usbdrd-phy",
.data = &exynos990_usbdrd_phy
+ }, {
+ .compatible = "samsung,exynosautov920-usb31drd-combo-ssphy",
+ .data = &exynosautov920_usb31drd_combo_ssphy
}, {
.compatible = "samsung,exynosautov920-usbdrd-combo-hsphy",
.data = &exynosautov920_usbdrd_combo_hsphy
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index 4923f9be3d1f..f96c773b85c9 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -690,4 +690,5 @@
/* exynosautov920 */
#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710)
+#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714)
#endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
--
2.34.1Hi Pritam,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on krzk/for-next linus/master v6.17-rc2 next-20250821]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Pritam-Manohar-Sutar/dt-bindings-phy-samsung-usb3-drd-phy-add-ExynosAutov920-HS-phy-compatible/20250821-153122
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250821073703.2498302-7-pritam.sutar%40samsung.com
patch subject: [PATCH v6 6/6] phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920
config: arc-randconfig-001-20250822 (https://download.01.org/0day-ci/archive/20250822/202508220553.lm7ExAxG-lkp@intel.com/config)
compiler: arc-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250822/202508220553.lm7ExAxG-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508220553.lm7ExAxG-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/phy/samsung/phy-exynos5-usbdrd.c: In function 'exynosautov920_usb31drd_cr_write':
>> drivers/phy/samsung/phy-exynos5-usbdrd.c:2167:17: warning: unused variable 'dev' [-Wunused-variable]
struct device *dev = phy_drd->dev;
^~~
drivers/phy/samsung/phy-exynos5-usbdrd.c: In function 'exynosautov920_usb31drd_port_phy_ready':
>> drivers/phy/samsung/phy-exynos5-usbdrd.c:2137:6: warning: 'reg' is used uninitialized in this function [-Wuninitialized]
reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
during RTL pass: mach
drivers/phy/samsung/phy-exynos5-usbdrd.c: In function 'exynos5_usbdrd_phy_probe':
drivers/phy/samsung/phy-exynos5-usbdrd.c:3056:1: internal compiler error: in arc_ifcvt, at config/arc/arc.c:9110
}
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <https://gcc.gnu.org/bugs/> for instructions.
vim +/dev +2167 drivers/phy/samsung/phy-exynos5-usbdrd.c
2125
2126 static void
2127 exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd)
2128 {
2129 struct device *dev = phy_drd->dev;
2130 void __iomem *reg_phy = phy_drd->reg_phy;
2131 static const unsigned int timeout_us = 20000;
2132 static const unsigned int sleep_us = 40;
2133 u32 reg;
2134 int err;
2135
2136 /* Clear cr_para_con */
> 2137 reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
2138 PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR);
2139 reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
2140 writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2141 writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1);
2142 writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
2143
2144 exynosautov920_usb31drd_cr_clk(phy_drd, true);
2145 exynosautov920_usb31drd_cr_clk(phy_drd, false);
2146
2147 /*
2148 * The maximum time from phy reset de-assertion to de-assertion of
2149 * tx/rx_ack can be as high as 5ms in fast simulation mode.
2150 * Time to phy ready is < 20ms
2151 */
2152 err = readl_poll_timeout(reg_phy +
2153 EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0,
2154 reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK),
2155 sleep_us, timeout_us);
2156 if (err)
2157 dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg);
2158
2159 reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
2160 writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2161 }
2162
2163 static void
2164 exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd,
2165 u16 addr, u16 data)
2166 {
> 2167 struct device *dev = phy_drd->dev;
2168 void __iomem *reg_phy = phy_drd->reg_phy;
2169 u32 cnt = 0;
2170 u32 reg;
2171
2172 /* Pre Clocking */
2173 reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2174 reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
2175 writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2176
2177 /*
2178 * tx clks must be available prior to assertion of tx req.
2179 * tx pstate p2 to p0 transition directly is not permitted.
2180 * tx clk ready must be asserted synchronously on tx clk prior
2181 * to internal transmit clk alignment sequence in the phy
2182 * when entering from p2 to p1 to p0.
2183 */
2184 do {
2185 exynosautov920_usb31drd_cr_clk(phy_drd, true);
2186 exynosautov920_usb31drd_cr_clk(phy_drd, false);
2187 cnt++;
2188 } while (cnt < 15);
2189
2190 reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
2191 writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2192
2193 /*
2194 * tx data path is active when tx lane is in p0 state
2195 * and tx data en asserted. enable cr_para_wr_en.
2196 */
2197 reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
2198 reg &= ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA;
2199 reg |= FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) |
2200 PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN;
2201 writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
2202
2203 /* write addr */
2204 reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2205 reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR;
2206 reg |= FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) |
2207 PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
2208 PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
2209 writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2210
2211 /* check cr_para_ack*/
2212 cnt = 0;
2213 do {
2214 /*
2215 * data symbols are captured by phy on rising edge of the
2216 * tx_clk when tx data enabled.
2217 * completion of the write cycle is acknowledged by assertion
2218 * of the cr_para_ack.
2219 */
2220 exynosautov920_usb31drd_cr_clk(phy_drd, true);
2221 reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
2222 if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK))
2223 break;
2224
2225 exynosautov920_usb31drd_cr_clk(phy_drd, false);
2226
2227 /*
2228 * wait for minimum of 10 cr_para_clk cycles after phy reset
2229 * is negated, before accessing control regs to allow for
2230 * internal resets.
2231 */
2232 cnt++;
2233 } while (cnt < 10);
2234
2235 if (cnt < 10)
2236 exynosautov920_usb31drd_cr_clk(phy_drd, false);
2237 }
2238
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi,
> -----Original Message-----
> From: kernel test robot <lkp@intel.com>
> Sent: 22 August 2025 02:58 AM
> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>; vkoul@kernel.org;
> kishon@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; alim.akhtar@samsung.com; andre.draszik@linaro.org;
> peter.griffin@linaro.org; kauschluss@disroot.org;
> ivo.ivanov.ivanov1@gmail.com; igor.belwon@mentallysanemainliners.org;
> johan@kernel.org; m.szyprowski@samsung.com; s.nawrocki@samsung.com
> Cc: oe-kbuild-all@lists.linux.dev; linux-phy@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org;
> rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v6 6/6] phy: exynos5-usbdrd: support SS combo phy for
> ExynosAutov920
>
> Hi Pritam,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on robh/for-next] [also build test WARNING on
> krzk/for-next linus/master v6.17-rc2 next-20250821] [If your patch is
applied
> to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://protect2.fireeye.com/v1/url?k=07116f39-666ac5ae-0710e476-
> 74fe4860001d-17dff89291ad3b5b&q=1&e=45b4f292-bcb1-4614-86a0-
> c790a47fb814&u=https%3A%2F%2Fgithub.com%2Fintel-lab-
> lkp%2Flinux%2Fcommits%2FPritam-Manohar-Sutar%2Fdt-bindings-phy-
> samsung-usb3-drd-phy-add-ExynosAutov920-HS-phy-
> compatible%2F20250821-153122
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
for-
> next
> patch link: https://lore.kernel.org/r/20250821073703.2498302-7-
> pritam.sutar%40samsung.com
> patch subject: [PATCH v6 6/6] phy: exynos5-usbdrd: support SS combo phy
> for ExynosAutov920
> config: arc-randconfig-001-20250822 (https://download.01.org/0day-
> ci/archive/20250822/202508220553.lm7ExAxG-lkp@intel.com/config)
> compiler: arc-linux-gcc (GCC) 8.5.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-
> ci/archive/20250822/202508220553.lm7ExAxG-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new
version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes:
> | https://lore.kernel.org/oe-kbuild-all/202508220553.lm7ExAxG-lkp@intel.
> | com/
>
> All warnings (new ones prefixed by >>):
>
> drivers/phy/samsung/phy-exynos5-usbdrd.c: In function
> 'exynosautov920_usb31drd_cr_write':
> >> drivers/phy/samsung/phy-exynos5-usbdrd.c:2167:17: warning: unused
> >> variable 'dev' [-Wunused-variable]
> struct device *dev = phy_drd->dev;
> ^~~
> drivers/phy/samsung/phy-exynos5-usbdrd.c: In function
> 'exynosautov920_usb31drd_port_phy_ready':
> >> drivers/phy/samsung/phy-exynos5-usbdrd.c:2137:6: warning: 'reg' is
> >> used uninitialized in this function [-Wuninitialized]
> reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
> ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR);
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> during RTL pass: mach
> drivers/phy/samsung/phy-exynos5-usbdrd.c: In function
> 'exynos5_usbdrd_phy_probe':
> drivers/phy/samsung/phy-exynos5-usbdrd.c:3056:1: internal compiler
> error: in arc_ifcvt, at config/arc/arc.c:9110
> }
> ^
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See <https://gcc.gnu.org/bugs/> for instructions.
>
>
> vim +/dev +2167 drivers/phy/samsung/phy-exynos5-usbdrd.c
>
> 2125
> 2126 static void
> 2127 exynosautov920_usb31drd_port_phy_ready(struct
> exynos5_usbdrd_phy *phy_drd)
> 2128 {
> 2129 struct device *dev = phy_drd->dev;
> 2130 void __iomem *reg_phy = phy_drd->reg_phy;
> 2131 static const unsigned int timeout_us = 20000;
> 2132 static const unsigned int sleep_us = 40;
> 2133 u32 reg;
> 2134 int err;
> 2135
> 2136 /* Clear cr_para_con */
> > 2137 reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
> 2138
> PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR);
> 2139 reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
> 2140 writel(reg, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2141 writel(0x0, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1);
> 2142 writel(0x0, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
> 2143
> 2144 exynosautov920_usb31drd_cr_clk(phy_drd, true);
> 2145 exynosautov920_usb31drd_cr_clk(phy_drd, false);
> 2146
> 2147 /*
> 2148 * The maximum time from phy reset de-assertion to
de-
> assertion of
> 2149 * tx/rx_ack can be as high as 5ms in fast
simulation mode.
> 2150 * Time to phy ready is < 20ms
> 2151 */
> 2152 err = readl_poll_timeout(reg_phy +
> 2153
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0,
> 2154 reg, !(reg &
> PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK),
> 2155 sleep_us, timeout_us);
> 2156 if (err)
> 2157 dev_err(dev, "timed out waiting for
rx/tx_ack:
> %#.8x\n", reg);
> 2158
> 2159 reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
> 2160 writel(reg, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2161 }
> 2162
> 2163 static void
> 2164 exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy
> *phy_drd,
> 2165 u16 addr, u16 data)
> 2166 {
> > 2167 struct device *dev = phy_drd->dev;
> 2168 void __iomem *reg_phy = phy_drd->reg_phy;
> 2169 u32 cnt = 0;
> 2170 u32 reg;
> 2171
> 2172 /* Pre Clocking */
> 2173 reg = readl(reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2174 reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
> 2175 writel(reg, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2176
> 2177 /*
> 2178 * tx clks must be available prior to assertion of
tx req.
> 2179 * tx pstate p2 to p0 transition directly is not
permitted.
> 2180 * tx clk ready must be asserted synchronously on tx
clk prior
> 2181 * to internal transmit clk alignment sequence in
the phy
> 2182 * when entering from p2 to p1 to p0.
> 2183 */
> 2184 do {
> 2185 exynosautov920_usb31drd_cr_clk(phy_drd,
true);
> 2186 exynosautov920_usb31drd_cr_clk(phy_drd,
false);
> 2187 cnt++;
> 2188 } while (cnt < 15);
> 2189
> 2190 reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
> 2191 writel(reg, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2192
> 2193 /*
> 2194 * tx data path is active when tx lane is in p0
state
> 2195 * and tx data en asserted. enable cr_para_wr_en.
> 2196 */
> 2197 reg = readl(reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
> 2198 reg &= ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA;
> 2199 reg |=
> FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) |
> 2200 PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN;
> 2201 writel(reg, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
> 2202
> 2203 /* write addr */
> 2204 reg = readl(reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2205 reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR;
> 2206 reg |=
> FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) |
> 2207 PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
> 2208 PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
> 2209 writel(reg, reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2210
> 2211 /* check cr_para_ack*/
> 2212 cnt = 0;
> 2213 do {
> 2214 /*
> 2215 * data symbols are captured by phy on
rising edge of
> the
> 2216 * tx_clk when tx data enabled.
> 2217 * completion of the write cycle is
acknowledged by
> assertion
> 2218 * of the cr_para_ack.
> 2219 */
> 2220 exynosautov920_usb31drd_cr_clk(phy_drd,
true);
> 2221 reg = readl(reg_phy +
> EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
> 2222 if ((reg &
> PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK))
> 2223 break;
> 2224
> 2225 exynosautov920_usb31drd_cr_clk(phy_drd,
false);
> 2226
> 2227 /*
> 2228 * wait for minimum of 10 cr_para_clk cycles
after phy
> reset
> 2229 * is negated, before accessing control regs
to allow
> for
> 2230 * internal resets.
> 2231 */
> 2232 cnt++;
> 2233 } while (cnt < 10);
> 2234
> 2235 if (cnt < 10)
> 2236 exynosautov920_usb31drd_cr_clk(phy_drd,
false);
> 2237 }
> 2238
>
> --
> 0-DAY CI Kernel Test Service
> https://protect2.fireeye.com/v1/url?k=96757503-f70edf94-9674fe4c-
> 74fe4860001d-38e3f56dae8e119d&q=1&e=45b4f292-bcb1-4614-86a0-
> c790a47fb814&u=https%3A%2F%2Fgithub.com%2Fintel%2Flkp-tests%2Fwiki
Will post v7 with the fixes for these warnings.
Thank you.
Regards,
Pritam
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