Reuse the available cacheinfo helpers instead of open-coding masks and
shifts in cacheinfo_amd_init_llc_id().

This series has been tested on top of tip:x86/cpu at commit 6a42c31ef324
("x86/cpu: Rename and move CPU model entry for Diamond Rapids") with no
changes being observed in "/sys/kernel/debug/x86/topo/" on a 3rd
Generation EPYC platform.

---
K Prateek Nayak (2):
  x86/cpu/cacheinfo: Convert get_cache_id() to use APIC ID and return
    Cache ID
  x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using
    _cpuid4_info

 arch/x86/kernel/cpu/cacheinfo.c | 47 ++++++++++++++-------------------
 1 file changed, 20 insertions(+), 27 deletions(-)


base-commit: 6a42c31ef324476fb304e137fe71870fcc538c88
-- 
2.34.1

Hi,

On Thu, 21 Aug 2025, K Prateek Nayak wrote:
>
> Reuse the available cacheinfo helpers instead of open-coding masks and
> shifts in cacheinfo_amd_init_llc_id().
>
> This series has been tested on top of tip:x86/cpu at commit 6a42c31ef324
> ("x86/cpu: Rename and move CPU model entry for Diamond Rapids") with no
> changes being observed in "/sys/kernel/debug/x86/topo/" on a 3rd
> Generation EPYC platform.
>

I had to merge the diff of the two patches to get what was going on.

My only comment would be:

> --- a/arch/x86/kernel/cpu/cacheinfo.c
> +++ b/arch/x86/kernel/cpu/cacheinfo.c
> ...
> +/*
> + * The max shared threads number comes from CPUID(0x4) EAX[25-14] with input
> + * ECX as cache index. Then right shift apicid by the number's order to get
> + * cache id for this cache node.
> + */
> +static unsigned int get_cache_id(u32 apicid, struct _cpuid4_info *id4)
> +{
> +	unsigned long num_threads_sharing;
> +	int index_msb;
> +
> +	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
> +	index_msb = get_count_order(num_threads_sharing);
> +	return apicid >> index_msb;
> +}
> +
...
> -/*
> - * The max shared threads number comes from CPUID(0x4) EAX[25-14] with input
> - * ECX as cache index. Then right shift apicid by the number's order to get
> - * cache id for this cache node.
> - */
> -static void get_cache_id(int cpu, struct _cpuid4_info *id4)
> -{
> -	struct cpuinfo_x86 *c = &cpu_data(cpu);
> -	unsigned long num_threads_sharing;
> -	int index_msb;
> -
> -	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
> -	index_msb = get_count_order(num_threads_sharing);
> -	id4->id = c->topo.apicid >> index_msb;
> -}
> -
...

Since you don't write to 'id4' anymore, please make the pointer constant.
It helps with code comprehension: from a quick glance, one knows that the
function does not write to the passed structure.

Other than that, and possibly merging the two patches (if you want to):

Acked-by: Ahmed S. Darwish <darwi@linutronix.de>

Thanks!

On Thu, Aug 21, 2025 at 11:53:41AM +0200, Ahmed S. Darwish wrote:
> Since you don't write to 'id4' anymore, please make the pointer constant.
> It helps with code comprehension: from a quick glance, one knows that the
> function does not write to the passed structure.
> 
> Other than that, and possibly merging the two patches (if you want to):
> 
> Acked-by: Ahmed S. Darwish <darwi@linutronix.de>
> 
> Thanks!

Makes sense, final result still looks readable:

From: K Prateek Nayak <kprateek.nayak@amd.com>
Date: Thu, 21 Aug 2025 05:19:09 +0000
Subject: [PATCH] x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using
 _cpuid4_info

struct _cpuid4_info has the same layout as the CPUID leaf 0x8000001d.
Use the encoded definition and amd_fill_cpuid4_info(), get_cache_id()
helpers instead of open coding masks and shifts to calculate the llc_id.

cacheinfo_amd_init_llc_id() is only called on AMD systems that support
X86_FEATURE_TOPOEXT and amd_fill_cpuid4_info() uses the information from
CPUID leaf 0x8000001d on all these systems which is consistent with the
current open coded implementation.

While at it, avoid reading  cpu_data() every time get_cache_id() is
called and instead pass the APIC ID necessary to return the
_cpuid4_info.id from get_cache_id().

No functional changes intended.

  [ bp: do what Ahmed suggests: merge into one patch, make id4 ptr
    const. ]

Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://lore.kernel.org/20250821051910.7351-2-kprateek.nayak@amd.com
---
 arch/x86/kernel/cpu/cacheinfo.c | 48 +++++++++++++++------------------
 1 file changed, 21 insertions(+), 27 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index adfa7e8bb865..51a95b07831f 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -289,6 +289,22 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c)
 	return i;
 }
 
+/*
+ * The max shared threads number comes from CPUID(0x4) EAX[25-14] with input
+ * ECX as cache index. Then right shift apicid by the number's order to get
+ * cache id for this cache node.
+ */
+static unsigned int get_cache_id(u32 apicid, const struct _cpuid4_info *id4)
+{
+	unsigned long num_threads_sharing;
+	int index_msb;
+
+	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
+	index_msb = get_count_order(num_threads_sharing);
+
+	return apicid >> index_msb;
+}
+
 /*
  * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist.
  */
@@ -312,18 +328,11 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
 		 * Newer families: LLC ID is calculated from the number
 		 * of threads sharing the L3 cache.
 		 */
-		u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
 		u32 llc_index = find_num_cache_leaves(c) - 1;
+		struct _cpuid4_info id4 = {};
 
-		cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
-		if (eax)
-			num_sharing_cache = ((eax >> 14) & 0xfff) + 1;
-
-		if (num_sharing_cache) {
-			int index_msb = get_count_order(num_sharing_cache);
-
-			c->topo.llc_id = c->topo.apicid >> index_msb;
-		}
+		if (!amd_fill_cpuid4_info(llc_index, &id4))
+			c->topo.llc_id = get_cache_id(c->topo.apicid, &id4);
 	}
 }
 
@@ -598,27 +607,12 @@ int init_cache_level(unsigned int cpu)
 	return 0;
 }
 
-/*
- * The max shared threads number comes from CPUID(0x4) EAX[25-14] with input
- * ECX as cache index. Then right shift apicid by the number's order to get
- * cache id for this cache node.
- */
-static void get_cache_id(int cpu, struct _cpuid4_info *id4)
-{
-	struct cpuinfo_x86 *c = &cpu_data(cpu);
-	unsigned long num_threads_sharing;
-	int index_msb;
-
-	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
-	index_msb = get_count_order(num_threads_sharing);
-	id4->id = c->topo.apicid >> index_msb;
-}
-
 int populate_cache_leaves(unsigned int cpu)
 {
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	struct cacheinfo *ci = this_cpu_ci->info_list;
 	u8 cpu_vendor = boot_cpu_data.x86_vendor;
+	u32 apicid = cpu_data(cpu).topo.apicid;
 	struct amd_northbridge *nb = NULL;
 	struct _cpuid4_info id4 = {};
 	int idx, ret;
@@ -628,7 +622,7 @@ int populate_cache_leaves(unsigned int cpu)
 		if (ret)
 			return ret;
 
-		get_cache_id(cpu, &id4);
+		id4.id = get_cache_id(apicid, &id4);
 
 		if (cpu_vendor == X86_VENDOR_AMD || cpu_vendor == X86_VENDOR_HYGON)
 			nb = amd_init_l3_cache(idx);
-- 
2.51.0

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

On Thu, Aug 21, 2025 at 05:19:08AM +0000, K Prateek Nayak wrote:
> Reuse the available cacheinfo helpers instead of open-coding masks and
> shifts in cacheinfo_amd_init_llc_id().
> 
> This series has been tested on top of tip:x86/cpu at commit 6a42c31ef324

Yeah, for the future - no need to do it now - pls test patches for tip only
ontop of tip/master.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette