1. Patchew
  2. linux
  3. [PATCH v4 00/13] Enable display support for STM32MP25
  4. View patch

[PATCH v4 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC

Raphael Gallais-Pou posted 13 patches 5 months, 3 weeks ago
There is a newer version of this series
[PATCH v4 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC
Posted by Raphael Gallais-Pou 5 months, 3 weeks ago 
From: Yannick Fertre <yannick.fertre@foss.st.com>

STM32MP25 SoC features a new version of the LTDC IP.  Add its compatible
to the list of device to probe and implement its quirks.

This hardware supports a pad frequency of 150MHz and a peripheral bus
clock.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
---
 drivers/gpu/drm/stm/drv.c  | 12 +++++++++++-
 drivers/gpu/drm/stm/ltdc.c | 38 +++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/stm/ltdc.h |  5 +++++
 3 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..ab00d1a6140cc32e71e10abc82f7956328b518e3 100644
--- a/drivers/gpu/drm/stm/drv.c
+++ b/drivers/gpu/drm/stm/drv.c
@@ -236,8 +236,18 @@ static void stm_drm_platform_shutdown(struct platform_device *pdev)
 	drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
 }
 
+static struct ltdc_plat_data stm_drm_plat_data = {
+	.pad_max_freq_hz = 90000000,
+};
+
+static struct ltdc_plat_data stm_drm_plat_data_mp25 = {
+	.pad_max_freq_hz = 150000000,
+};
+
 static const struct of_device_id drv_dt_ids[] = {
-	{ .compatible = "st,stm32-ltdc"},
+	{ .compatible = "st,stm32-ltdc", .data = &stm_drm_plat_data, },
+	{ .compatible = "st,stm32mp251-ltdc", .data = &stm_drm_plat_data_mp25, },
+	{ .compatible = "st,stm32mp255-ltdc", .data = &stm_drm_plat_data_mp25, },
 	{ /* end node */ },
 };
 MODULE_DEVICE_TABLE(of, drv_dt_ids);
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index ba315c66a04d72758b9d3cfcd842432877f66d3a..17548dd3484a0a3e1015c58c752b80f8892a0ff7 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/media-bus-format.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/of_graph.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
@@ -51,6 +52,7 @@
 #define HWVER_10300 0x010300
 #define HWVER_20101 0x020101
 #define HWVER_40100 0x040100
+#define HWVER_40101 0x040101
 
 /*
  * The address of some registers depends on the HW version: such registers have
@@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev)
 {
 	struct ltdc_device *ldev = ddev->dev_private;
 	u32 bus_width_log2, lcr, gc2r;
+	const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev);
 
 	/*
 	 * at least 1 layer must be managed & the number of layers
@@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev)
 	ldev->caps.bus_width = 8 << bus_width_log2;
 	regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
 
+	ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz;
+
 	switch (ldev->caps.hw_version) {
 	case HWVER_10200:
 	case HWVER_10300:
@@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev)
 		 * does not work on 2nd layer.
 		 */
 		ldev->caps.non_alpha_only_l1 = true;
-		ldev->caps.pad_max_freq_hz = 90000000;
 		if (ldev->caps.hw_version == HWVER_10200)
 			ldev->caps.pad_max_freq_hz = 65000000;
 		ldev->caps.nb_irq = 2;
@@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev)
 		ldev->caps.fifo_threshold = false;
 		break;
 	case HWVER_40100:
+	case HWVER_40101:
 		ldev->caps.layer_ofs = LAY_OFS_1;
 		ldev->caps.layer_regs = ltdc_layer_regs_a2;
 		ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
@@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev)
 		ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
 		ldev->caps.pix_fmt_flex = true;
 		ldev->caps.non_alpha_only_l1 = false;
-		ldev->caps.pad_max_freq_hz = 90000000;
 		ldev->caps.nb_irq = 2;
 		ldev->caps.ycbcr_input = true;
 		ldev->caps.ycbcr_output = true;
@@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev)
 
 	DRM_DEBUG_DRIVER("\n");
 	clk_disable_unprepare(ldev->pixel_clk);
+	if (ldev->bus_clk)
+		clk_disable_unprepare(ldev->bus_clk);
 }
 
 int ltdc_resume(struct drm_device *ddev)
@@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev)
 		return ret;
 	}
 
-	return 0;
+	if (ldev->bus_clk) {
+		ret = clk_prepare_enable(ldev->bus_clk);
+		if (ret)
+			drm_err(ddev, "failed to enable bus clock (%d)\n", ret);
+	}
+
+	return ret;
 }
 
 int ltdc_load(struct drm_device *ddev)
@@ -1922,6 +1934,20 @@ int ltdc_load(struct drm_device *ddev)
 		return -ENODEV;
 	}
 
+	if (of_device_is_compatible(np, "st,stm32mp251-ltdc") ||
+	    of_device_is_compatible(np, "st,stm32mp255-ltdc")) {
+		ldev->bus_clk = devm_clk_get(dev, "bus");
+		if (IS_ERR(ldev->bus_clk))
+			return dev_err_probe(dev, PTR_ERR(ldev->bus_clk),
+					     "Unable to get bus clock\n");
+
+		ret = clk_prepare_enable(ldev->bus_clk);
+		if (ret) {
+			drm_err(ddev, "Unable to prepare bus clock\n");
+			return ret;
+		}
+	}
+
 	/* Get endpoints if any */
 	for (i = 0; i < nb_endpoints; i++) {
 		ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
@@ -2034,6 +2060,9 @@ int ltdc_load(struct drm_device *ddev)
 
 	clk_disable_unprepare(ldev->pixel_clk);
 
+	if (ldev->bus_clk)
+		clk_disable_unprepare(ldev->bus_clk);
+
 	pinctrl_pm_select_sleep_state(ddev->dev);
 
 	pm_runtime_enable(ddev->dev);
@@ -2042,6 +2071,9 @@ int ltdc_load(struct drm_device *ddev)
 err:
 	clk_disable_unprepare(ldev->pixel_clk);
 
+	if (ldev->bus_clk)
+		clk_disable_unprepare(ldev->bus_clk);
+
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -40,10 +40,15 @@ struct fps_info {
 	ktime_t last_timestamp;
 };
 
+struct ltdc_plat_data {
+	int pad_max_freq_hz;	/* max frequency supported by pad */
+};
+
 struct ltdc_device {
 	void __iomem *regs;
 	struct regmap *regmap;
 	struct clk *pixel_clk;	/* lcd pixel clock */
+	struct clk *bus_clk;	/* bus clock */
 	struct mutex err_lock;	/* protecting error_status */
 	struct ltdc_caps caps;
 	u32 irq_status;

-- 
2.25.1
Re: [PATCH v4 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC
Posted by Yannick FERTRE 5 months, 3 weeks ago 
Hi Raphael,

Thanks for the patch.

Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>

Le 21/08/2025 à 13:08, Raphael Gallais-Pou a écrit :
> From: Yannick Fertre <yannick.fertre@foss.st.com>
>
> STM32MP25 SoC features a new version of the LTDC IP.  Add its compatible
> to the list of device to probe and implement its quirks.
>
> This hardware supports a pad frequency of 150MHz and a peripheral bus
> clock.
>
> Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
> Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
> ---
>   drivers/gpu/drm/stm/drv.c  | 12 +++++++++++-
>   drivers/gpu/drm/stm/ltdc.c | 38 +++++++++++++++++++++++++++++++++++---
>   drivers/gpu/drm/stm/ltdc.h |  5 +++++
>   3 files changed, 51 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
> index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..ab00d1a6140cc32e71e10abc82f7956328b518e3 100644
> --- a/drivers/gpu/drm/stm/drv.c
> +++ b/drivers/gpu/drm/stm/drv.c
> @@ -236,8 +236,18 @@ static void stm_drm_platform_shutdown(struct platform_device *pdev)
>   	drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
>   }
>   
> +static struct ltdc_plat_data stm_drm_plat_data = {
> +	.pad_max_freq_hz = 90000000,
> +};
> +
> +static struct ltdc_plat_data stm_drm_plat_data_mp25 = {
> +	.pad_max_freq_hz = 150000000,
> +};
> +
>   static const struct of_device_id drv_dt_ids[] = {
> -	{ .compatible = "st,stm32-ltdc"},
> +	{ .compatible = "st,stm32-ltdc", .data = &stm_drm_plat_data, },
> +	{ .compatible = "st,stm32mp251-ltdc", .data = &stm_drm_plat_data_mp25, },
> +	{ .compatible = "st,stm32mp255-ltdc", .data = &stm_drm_plat_data_mp25, },
>   	{ /* end node */ },
>   };
>   MODULE_DEVICE_TABLE(of, drv_dt_ids);
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index ba315c66a04d72758b9d3cfcd842432877f66d3a..17548dd3484a0a3e1015c58c752b80f8892a0ff7 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -14,6 +14,7 @@
>   #include <linux/interrupt.h>
>   #include <linux/media-bus-format.h>
>   #include <linux/module.h>
> +#include <linux/of.h>
>   #include <linux/of_graph.h>
>   #include <linux/pinctrl/consumer.h>
>   #include <linux/platform_device.h>
> @@ -51,6 +52,7 @@
>   #define HWVER_10300 0x010300
>   #define HWVER_20101 0x020101
>   #define HWVER_40100 0x040100
> +#define HWVER_40101 0x040101
>   
>   /*
>    * The address of some registers depends on the HW version: such registers have
> @@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev)
>   {
>   	struct ltdc_device *ldev = ddev->dev_private;
>   	u32 bus_width_log2, lcr, gc2r;
> +	const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev);
>   
>   	/*
>   	 * at least 1 layer must be managed & the number of layers
> @@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev)
>   	ldev->caps.bus_width = 8 << bus_width_log2;
>   	regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
>   
> +	ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz;
> +
>   	switch (ldev->caps.hw_version) {
>   	case HWVER_10200:
>   	case HWVER_10300:
> @@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev)
>   		 * does not work on 2nd layer.
>   		 */
>   		ldev->caps.non_alpha_only_l1 = true;
> -		ldev->caps.pad_max_freq_hz = 90000000;
>   		if (ldev->caps.hw_version == HWVER_10200)
>   			ldev->caps.pad_max_freq_hz = 65000000;
>   		ldev->caps.nb_irq = 2;
> @@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev)
>   		ldev->caps.fifo_threshold = false;
>   		break;
>   	case HWVER_40100:
> +	case HWVER_40101:
>   		ldev->caps.layer_ofs = LAY_OFS_1;
>   		ldev->caps.layer_regs = ltdc_layer_regs_a2;
>   		ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
> @@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev)
>   		ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
>   		ldev->caps.pix_fmt_flex = true;
>   		ldev->caps.non_alpha_only_l1 = false;
> -		ldev->caps.pad_max_freq_hz = 90000000;
>   		ldev->caps.nb_irq = 2;
>   		ldev->caps.ycbcr_input = true;
>   		ldev->caps.ycbcr_output = true;
> @@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev)
>   
>   	DRM_DEBUG_DRIVER("\n");
>   	clk_disable_unprepare(ldev->pixel_clk);
> +	if (ldev->bus_clk)
> +		clk_disable_unprepare(ldev->bus_clk);
>   }
>   
>   int ltdc_resume(struct drm_device *ddev)
> @@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev)
>   		return ret;
>   	}
>   
> -	return 0;
> +	if (ldev->bus_clk) {
> +		ret = clk_prepare_enable(ldev->bus_clk);
> +		if (ret)
> +			drm_err(ddev, "failed to enable bus clock (%d)\n", ret);
> +	}
> +
> +	return ret;
>   }
>   
>   int ltdc_load(struct drm_device *ddev)
> @@ -1922,6 +1934,20 @@ int ltdc_load(struct drm_device *ddev)
>   		return -ENODEV;
>   	}
>   
> +	if (of_device_is_compatible(np, "st,stm32mp251-ltdc") ||
> +	    of_device_is_compatible(np, "st,stm32mp255-ltdc")) {
> +		ldev->bus_clk = devm_clk_get(dev, "bus");
> +		if (IS_ERR(ldev->bus_clk))
> +			return dev_err_probe(dev, PTR_ERR(ldev->bus_clk),
> +					     "Unable to get bus clock\n");
> +
> +		ret = clk_prepare_enable(ldev->bus_clk);
> +		if (ret) {
> +			drm_err(ddev, "Unable to prepare bus clock\n");
> +			return ret;
> +		}
> +	}
> +
>   	/* Get endpoints if any */
>   	for (i = 0; i < nb_endpoints; i++) {
>   		ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
> @@ -2034,6 +2060,9 @@ int ltdc_load(struct drm_device *ddev)
>   
>   	clk_disable_unprepare(ldev->pixel_clk);
>   
> +	if (ldev->bus_clk)
> +		clk_disable_unprepare(ldev->bus_clk);
> +
>   	pinctrl_pm_select_sleep_state(ddev->dev);
>   
>   	pm_runtime_enable(ddev->dev);
> @@ -2042,6 +2071,9 @@ int ltdc_load(struct drm_device *ddev)
>   err:
>   	clk_disable_unprepare(ldev->pixel_clk);
>   
> +	if (ldev->bus_clk)
> +		clk_disable_unprepare(ldev->bus_clk);
> +
>   	return ret;
>   }
>   
> diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
> index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1 100644
> --- a/drivers/gpu/drm/stm/ltdc.h
> +++ b/drivers/gpu/drm/stm/ltdc.h
> @@ -40,10 +40,15 @@ struct fps_info {
>   	ktime_t last_timestamp;
>   };
>   
> +struct ltdc_plat_data {
> +	int pad_max_freq_hz;	/* max frequency supported by pad */
> +};
> +
>   struct ltdc_device {
>   	void __iomem *regs;
>   	struct regmap *regmap;
>   	struct clk *pixel_clk;	/* lcd pixel clock */
> +	struct clk *bus_clk;	/* bus clock */
>   	struct mutex err_lock;	/* protecting error_status */
>   	struct ltdc_caps caps;
>   	u32 irq_status;
>

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.