[v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

[PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Prabhakar 3 months, 4 weeks ago

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
[0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
0x8, not 0x20 as previously defined.

Offset 0x20 actually maps to the Port Trigger Control Register (PTCTRL),
which controls PTP_MODE[3:0] and RGMII_CLKSEL[4]. Using this incorrect
definition prevented the driver from configuring the SW_MODE[4:0] bits
in MODCTRL, which control the internal connection of Ethernet ports. As
a result, the MIIC could not be switched into the correct mode, leading
to link setup failures and non-functional Ethernet ports on affected
systems.

[0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571

Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
Cc: stable@kernel.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
v1->v2:
- Used correct subject prefix
- Updated commit message to clarify the issue.

Hi All,

I've just build-tested this patch and found this issue while working
on a similar IP on the Renesas RZ/T2H SoC where the MODCTRL register
offset is also at offset 0x8.

Cheers, Prabhakar
---
 drivers/net/pcs/pcs-rzn1-miic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index d79bb9b06cd2..ce73d9474d5b 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -19,7 +19,7 @@
 #define MIIC_PRCMD			0x0
 #define MIIC_ESID_CODE			0x4
 
-#define MIIC_MODCTRL			0x20
+#define MIIC_MODCTRL			0x8
 #define MIIC_MODCTRL_SW_MODE		GENMASK(4, 0)
 
 #define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
-- 
2.51.0

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Wolfram Sang 3 months, 3 weeks ago

On Wed, Aug 20, 2025 at 06:09:13PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> 0x8, not 0x20 as previously defined.
> 
> Offset 0x20 actually maps to the Port Trigger Control Register (PTCTRL),
> which controls PTP_MODE[3:0] and RGMII_CLKSEL[4]. Using this incorrect
> definition prevented the driver from configuring the SW_MODE[4:0] bits
> in MODCTRL, which control the internal connection of Ethernet ports. As
> a result, the MIIC could not be switched into the correct mode, leading
> to link setup failures and non-functional Ethernet ports on affected
> systems.
> 
> [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
> 
> Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> Cc: stable@kernel.org
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I had a look now. Because the bootloader of my N1D board already set up
MODCTRL correctly, this write to the wrong register went unnoticed. I
verified that the now correctly written value (depending on DT config)
matches the value previously set by the bootloader. As a result,
everything keeps working. We were lucky. Or unlucky. Depending how you
look at it.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for this fix!

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Lad, Prabhakar 3 months, 3 weeks ago

Hi Wolfram,

On Thu, Aug 28, 2025 at 11:25 AM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> On Wed, Aug 20, 2025 at 06:09:13PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> > According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> > [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> > 0x8, not 0x20 as previously defined.
> >
> > Offset 0x20 actually maps to the Port Trigger Control Register (PTCTRL),
> > which controls PTP_MODE[3:0] and RGMII_CLKSEL[4]. Using this incorrect
> > definition prevented the driver from configuring the SW_MODE[4:0] bits
> > in MODCTRL, which control the internal connection of Ethernet ports. As
> > a result, the MIIC could not be switched into the correct mode, leading
> > to link setup failures and non-functional Ethernet ports on affected
> > systems.
> >
> > [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
> >
> > Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> > Cc: stable@kernel.org
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> I had a look now. Because the bootloader of my N1D board already set up
> MODCTRL correctly, this write to the wrong register went unnoticed. I
> verified that the now correctly written value (depending on DT config)
> matches the value previously set by the bootloader. As a result,
> everything keeps working. We were lucky. Or unlucky. Depending how you
> look at it.
>
Thank you for testing it. I'll send a v3 soon with `net-next` dropped
from the subject.

Cheers,
Prabhakar

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Jakub Kicinski 3 months, 3 weeks ago

On Wed, 20 Aug 2025 18:09:13 +0100 Prabhakar wrote:
> Subject: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Hi Prabhakar!

AFAIU we're waiting for Wolfram to test (hopefully early) next week.
Could you repost in the meantime with [PATCH net v3] as the subject
prefix? If it's a fix it's not -next material.
-- 
pw-bot: cr

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Lad, Prabhakar 3 months, 3 weeks ago

Hi Jakub,

On Fri, Aug 22, 2025 at 1:22 AM Jakub Kicinski <kuba@kernel.org> wrote:
>
> On Wed, 20 Aug 2025 18:09:13 +0100 Prabhakar wrote:
> > Subject: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset
>
> Hi Prabhakar!
>
> AFAIU we're waiting for Wolfram to test (hopefully early) next week.
> Could you repost in the meantime with [PATCH net v3] as the subject
> prefix? If it's a fix it's not -next material.
>
Sure, I will do that.

Cheers,
Prabhakar

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Geert Uytterhoeven 3 months, 4 weeks ago

On Wed, 20 Aug 2025 at 19:09, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> 0x8, not 0x20 as previously defined.
>
> Offset 0x20 actually maps to the Port Trigger Control Register (PTCTRL),
> which controls PTP_MODE[3:0] and RGMII_CLKSEL[4]. Using this incorrect
> definition prevented the driver from configuring the SW_MODE[4:0] bits
> in MODCTRL, which control the internal connection of Ethernet ports. As
> a result, the MIIC could not be switched into the correct mode, leading
> to link setup failures and non-functional Ethernet ports on affected
> systems.
>
> [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
>
> Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> Cc: stable@kernel.org
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Wolfram Sang 3 months, 4 weeks ago

> I've just build-tested this patch and found this issue while working
> on a similar IP on the Renesas RZ/T2H SoC where the MODCTRL register
> offset is also at offset 0x8.

I can test this on affected hardware next week.

Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset

Posted by Russell King (Oracle) 3 months, 4 weeks ago

On Wed, Aug 20, 2025 at 06:09:13PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> 0x8, not 0x20 as previously defined.
> 
> Offset 0x20 actually maps to the Port Trigger Control Register (PTCTRL),
> which controls PTP_MODE[3:0] and RGMII_CLKSEL[4]. Using this incorrect
> definition prevented the driver from configuring the SW_MODE[4:0] bits
> in MODCTRL, which control the internal connection of Ethernet ports. As
> a result, the MIIC could not be switched into the correct mode, leading
> to link setup failures and non-functional Ethernet ports on affected
> systems.
> 
> [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
> 
> Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> Cc: stable@kernel.org
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
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