The Motorcomm YT921x series is a family of Ethernet switches with up to
8 internal GbE PHYs and up to 2 GMACs.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
.../bindings/net/dsa/motorcomm,yt921x.yaml | 150 ++++++++++++++++++
1 file changed, 150 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml
diff --git a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml
new file mode 100644
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--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Motorcomm YT921x Ethernet switch family
+
+maintainers:
+ - David Yang <mmyangfl@gmail.com>
+
+description: |
+ The Motorcomm YT921x series is a family of Ethernet switches with up to 8
+ internal GbE PHYs and up to 2 GMACs, including:
+
+ - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port 8-9)
+ - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9)
+ - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9)
+ - YT9218N: 8 GbE PHYs (Port 0-7)
+ - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9)
+
+ Any port can be used as the CPU port.
+
+properties:
+ compatible:
+ const: motorcomm,yt9215
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ description: |
+ Internal MDIO bus for the internal GbE PHYs. PHYs 0-7 are used for Port
+ 0-7 respectively.
+
+ mdio-external:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ description: |
+ External MDIO bus to access external components. External PHYs for GMACs
+ (Port 8-9) are expected to be connected to the external MDIO bus in
+ vendor's reference design, but that is not a hard limitation from the
+ chip.
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@1d {
+ compatible = "motorcomm,yt9215";
+ /* default 0x1d, alternate 0x0 */
+ reg = <0x1d>;
+ reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: phy@0 {
+ reg = <0x0>;
+ };
+ };
+
+ mdio-external {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: phy@b {
+ reg = <0xb>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* phy-handle is optional for internal PHYs */
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&sw_phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-mode = "internal";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-mode = "internal";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ phy-mode = "internal";
+ };
+
+ /* CPU port */
+ port@8 {
+ reg = <8>;
+ phy-mode = "sgmii";
+ ethernet = <ð0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ asym-pause;
+ };
+ };
+
+ /* if external phy is connected to a MAC */
+ port@9 {
+ reg = <9>;
+ label = "wan";
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+ };
+ };
+ };
--
2.50.1> + switch@1d {
> + compatible = "motorcomm,yt9215";
> + /* default 0x1d, alternate 0x0 */
> + reg = <0x1d>;
Just curious, what does alternative 0x0 mean? Does this switch have
only one strapping pin for address, so it either uses address 0x1d or
0x0?
Andrew
On Thu, Aug 21, 2025 at 8:41 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > + switch@1d {
> > + compatible = "motorcomm,yt9215";
> > + /* default 0x1d, alternate 0x0 */
> > + reg = <0x1d>;
>
> Just curious, what does alternative 0x0 mean? Does this switch have
> only one strapping pin for address, so it either uses address 0x1d or
> 0x0?
>
> Andrew
Yes. I've seen this approach on other chips (offering two MDIO
phyaddrs), so this should be a common practice.
On Thu, Aug 21, 2025 at 08:50:18PM +0800, Yangfl wrote:
> On Thu, Aug 21, 2025 at 8:41 PM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > + switch@1d {
> > > + compatible = "motorcomm,yt9215";
> > > + /* default 0x1d, alternate 0x0 */
> > > + reg = <0x1d>;
> >
> > Just curious, what does alternative 0x0 mean? Does this switch have
> > only one strapping pin for address, so it either uses address 0x1d or
> > 0x0?
> >
> > Andrew
>
> Yes. I've seen this approach on other chips (offering two MDIO
> phyaddrs), so this should be a common practice.
If it only supports two addresses, you could add a constrain in the
binding that reg is [0x0, 0x1d].
Andrew
On Wed, Aug 20, 2025 at 03:54:14PM +0800, David Yang wrote: > The Motorcomm YT921x series is a family of Ethernet switches with up to > 8 internal GbE PHYs and up to 2 GMACs. Please use standard email subjects, so with the PATCH keyword in the title. 'git format-patch -vX' helps here to create proper versioned patches. Another useful tool is b4. Skipping the PATCH keyword makes filtering of emails more difficult thus making the review process less convenient. > > Signed-off-by: David Yang <mmyangfl@gmail.com> > --- > .../bindings/net/dsa/motorcomm,yt921x.yaml | 150 ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml ... > + mdio-external: > + $ref: /schemas/net/mdio.yaml# > + unevaluatedProperties: false > + description: | > + External MDIO bus to access external components. External PHYs for GMACs > + (Port 8-9) are expected to be connected to the external MDIO bus in > + vendor's reference design, but that is not a hard limitation from the > + chip. > + > +allOf: This goes after required: block. But don't resend just for that. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
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