[v3] x86 perf bug fixes and optimization

[Patch v3 0/7] x86 perf bug fixes and optimization

Posted by Dapeng Mi 1 month, 2 weeks ago

Changes:
  v2 -> v3:
  * Rebase to latest tip perf/core tree.
  * Rewrite commit message to explain why NULL access happens and
    refine code (Patch 3/7)
  * Refine commit message of patch 6/7
  * Dump counters bitmap instead of absolute counter in boot message
    (patch 7/7)

  v1 -> v2:
  * Rebase to 6.17-rc1.
  * No code changes.

Tests:
  * Run perf stats/record commands on Intel Sapphire Rapids platform, no
    issue is found.

History:
  v2: https://lore.kernel.org/all/20250811090034.51249-1-dapeng1.mi@linux.intel.com/ 
  v1:
  * Patch 1/6: https://lore.kernel.org/all/20250606111606.84350-1-dapeng1.mi@linux.intel.com/
  * Patch 2/6: https://lore.kernel.org/all/20250529080236.2552247-1-dapeng1.mi@linux.intel.com/
  * Patch 3/6: https://lore.kernel.org/all/20250718062602.21444-1-dapeng1.mi@linux.intel.com/
  * Patches 4-6/6: https://lore.kernel.org/all/20250717090302.11316-1-dapeng1.mi@linux.intel.com/

Dapeng Mi (7):
  perf/x86/intel: Use early_initcall() to hook bts_init()
  perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error
  perf/x86: Check if cpuc->events[*] pointer exists before accessing it
  perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag
  perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to
    BIT_ULL(48)
  perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into
    INTEL_FIXED_BITS_MASK
  perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()

 arch/x86/events/core.c                 | 16 +++++++++-------
 arch/x86/events/intel/bts.c            |  2 +-
 arch/x86/events/intel/core.c           | 21 +++++++++------------
 arch/x86/events/intel/ds.c             | 10 ++++++++++
 arch/x86/include/asm/msr-index.h       | 14 ++++++++------
 arch/x86/include/asm/perf_event.h      |  8 ++++++--
 arch/x86/kvm/pmu.h                     |  2 +-
 tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------
 8 files changed, 52 insertions(+), 35 deletions(-)


base-commit: 448f97fba9013ffa13f5dd82febd18836b189499
-- 
2.34.1

Re: [Patch v3 0/7] x86 perf bug fixes and optimization

Posted by Liang, Kan 1 month, 2 weeks ago


On 2025-08-19 7:30 p.m., Dapeng Mi wrote:
> Changes:
>   v2 -> v3:
>   * Rebase to latest tip perf/core tree.
>   * Rewrite commit message to explain why NULL access happens and
>     refine code (Patch 3/7)
>   * Refine commit message of patch 6/7
>   * Dump counters bitmap instead of absolute counter in boot message
>     (patch 7/7)
> 
>   v1 -> v2:
>   * Rebase to 6.17-rc1.
>   * No code changes.
> 
> Tests:
>   * Run perf stats/record commands on Intel Sapphire Rapids platform, no
>     issue is found.
> 
> History:
>   v2: https://lore.kernel.org/all/20250811090034.51249-1-dapeng1.mi@linux.intel.com/ 
>   v1:
>   * Patch 1/6: https://lore.kernel.org/all/20250606111606.84350-1-dapeng1.mi@linux.intel.com/
>   * Patch 2/6: https://lore.kernel.org/all/20250529080236.2552247-1-dapeng1.mi@linux.intel.com/
>   * Patch 3/6: https://lore.kernel.org/all/20250718062602.21444-1-dapeng1.mi@linux.intel.com/
>   * Patches 4-6/6: https://lore.kernel.org/all/20250717090302.11316-1-dapeng1.mi@linux.intel.com/
> 
> Dapeng Mi (7):
>   perf/x86/intel: Use early_initcall() to hook bts_init()
>   perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error
>   perf/x86: Check if cpuc->events[*] pointer exists before accessing it
>   perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag
>   perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to
>     BIT_ULL(48)
>   perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into
>     INTEL_FIXED_BITS_MASK
>   perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()
>

The series looks good to me.

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks,
Kan
>  arch/x86/events/core.c                 | 16 +++++++++-------
>  arch/x86/events/intel/bts.c            |  2 +-
>  arch/x86/events/intel/core.c           | 21 +++++++++------------
>  arch/x86/events/intel/ds.c             | 10 ++++++++++
>  arch/x86/include/asm/msr-index.h       | 14 ++++++++------
>  arch/x86/include/asm/perf_event.h      |  8 ++++++--
>  arch/x86/kvm/pmu.h                     |  2 +-
>  tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------
>  8 files changed, 52 insertions(+), 35 deletions(-)
> 
> 
> base-commit: 448f97fba9013ffa13f5dd82febd18836b189499

Re: [Patch v3 0/7] x86 perf bug fixes and optimization

Posted by Peter Zijlstra 1 month, 1 week ago

On Wed, Aug 20, 2025 at 08:55:24AM -0700, Liang, Kan wrote:

> > Dapeng Mi (7):
> >   perf/x86/intel: Use early_initcall() to hook bts_init()
> >   perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error
> >   perf/x86: Check if cpuc->events[*] pointer exists before accessing it
> >   perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag
> >   perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to
> >     BIT_ULL(48)
> >   perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into
> >     INTEL_FIXED_BITS_MASK
> >   perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()
> >
> 
> The series looks good to me.
> 
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

I've picked up all but patch 3 -- I really don't think that does the
right thing.

Re: [Patch v3 0/7] x86 perf bug fixes and optimization

Posted by Mi, Dapeng 1 month, 1 week ago

On 8/21/2025 9:39 PM, Peter Zijlstra wrote:
> On Wed, Aug 20, 2025 at 08:55:24AM -0700, Liang, Kan wrote:
>
>>> Dapeng Mi (7):
>>>   perf/x86/intel: Use early_initcall() to hook bts_init()
>>>   perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error
>>>   perf/x86: Check if cpuc->events[*] pointer exists before accessing it
>>>   perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag
>>>   perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to
>>>     BIT_ULL(48)
>>>   perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into
>>>     INTEL_FIXED_BITS_MASK
>>>   perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()
>>>
>> The series looks good to me.
>>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
> I've picked up all but patch 3 -- I really don't think that does the
> right thing.

Thanks. I would rewrite the patch 3 and aggregate it into the arch-PEBS
enabling series.