Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
on QCS615 Platform. This PHY supports both USB3 and DP functionality
over USB-C, with PHY mode switching capability. It does not support
combo mode.
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
---
.../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description:
+ The QMP PHY controller supports physical layer functionality for both
+ USB3 and DisplayPort over USB-C. While it enables mode switching
+ between USB3 and DisplayPort, but does not support combo mode.
+
+properties:
+ compatible:
+ enum:
+ - qcom,qcs615-qmp-usb3-dp-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: cfg_ahb
+ - const: ref
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy_phy
+ - const: dp_phy
+
+ vdda-phy-supply: true
+
+ vdda-pll-supply: true
+
+ "#clock-cells":
+ const: 1
+ description:
+ See include/dt-bindings/phy/phy-qcom-qmp.h
+
+ "#phy-cells":
+ const: 1
+ description:
+ See include/dt-bindings/phy/phy-qcom-qmp.h
+
+ qcom,tcsr-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to TCSR hardware block
+ - description: offset of the VLS CLAMP register
+ - items:
+ - description: phandle to TCSR hardware block
+ - description: offset of the DP PHY mode register
+ description: Clamp and PHY mode register present in the TCSR
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+ - "#clock-cells"
+ - "#phy-cells"
+ - qcom,tcsr-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ phy@88e8000 {
+ compatible = "qcom,qcs615-qmp-usb3-dp-phy";
+ reg = <0x88e8000 0x2000>;
+
+ clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
+ <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
+ reset-names = "phy_phy",
+ "dp_phy";
+
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ qcom,tcsr-reg = <&tcsr 0xbff0>,
+ <&tcsr 0xb24c>;
+ };
--
2.34.1On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote:
> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
> on QCS615 Platform. This PHY supports both USB3 and DP functionality
> over USB-C, with PHY mode switching capability. It does not support
> combo mode.
>
> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
> ---
> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
> +
> +maintainers:
> + - Vinod Koul <vkoul@kernel.org>
No, this should be someone who has the h/w.
> +
> +description:
> + The QMP PHY controller supports physical layer functionality for both
> + USB3 and DisplayPort over USB-C. While it enables mode switching
> + between USB3 and DisplayPort, but does not support combo mode.
Wrap at 80 chars.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qcs615-qmp-usb3-dp-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: cfg_ahb
> + - const: ref
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: phy_phy
phy_phy?
> + - const: dp_phy
> +
> + vdda-phy-supply: true
> +
> + vdda-pll-supply: true
> +
> + "#clock-cells":
> + const: 1
> + description:
> + See include/dt-bindings/phy/phy-qcom-qmp.h
> +
> + "#phy-cells":
> + const: 1
> + description:
> + See include/dt-bindings/phy/phy-qcom-qmp.h
> +
> + qcom,tcsr-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to TCSR hardware block
> + - description: offset of the VLS CLAMP register
> + - items:
> + - description: phandle to TCSR hardware block
> + - description: offset of the DP PHY mode register
> + description: Clamp and PHY mode register present in the TCSR
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> + - "#clock-cells"
> + - "#phy-cells"
> + - qcom,tcsr-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + phy@88e8000 {
> + compatible = "qcom,qcs615-qmp-usb3-dp-phy";
> + reg = <0x88e8000 0x2000>;
> +
> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
> + reset-names = "phy_phy",
> + "dp_phy";
> +
> + vdda-phy-supply = <&vreg_l11a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + qcom,tcsr-reg = <&tcsr 0xbff0>,
> + <&tcsr 0xb24c>;
> + };
>
> --
> 2.34.1
>
On 8/22/2025 10:22 PM, Rob Herring wrote:
> On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote:
>> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
>> on QCS615 Platform. This PHY supports both USB3 and DP functionality
>> over USB-C, with PHY mode switching capability. It does not support
>> combo mode.
>>
>> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
>> ---
>> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
>> 1 file changed, 108 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
>> +
>> +maintainers:
>> + - Vinod Koul <vkoul@kernel.org>
> No, this should be someone who has the h/w.
I have discussed with Bjorn offline. In the next version, I’ll update myself as
the maintainer for this dt-binding.
>> +
>> +description:
>> + The QMP PHY controller supports physical layer functionality for both
>> + USB3 and DisplayPort over USB-C. While it enables mode switching
>> + between USB3 and DisplayPort, but does not support combo mode.
> Wrap at 80 chars.
Ok, will update next patch.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,qcs615-qmp-usb3-dp-phy
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 2
>> +
>> + clock-names:
>> + items:
>> + - const: cfg_ahb
>> + - const: ref
>> +
>> + resets:
>> + maxItems: 2
>> +
>> + reset-names:
>> + items:
>> + - const: phy_phy
> phy_phy?
>
>> + - const: dp_phy
>> +
>> + vdda-phy-supply: true
>> +
>> + vdda-pll-supply: true
>> +
>> + "#clock-cells":
>> + const: 1
>> + description:
>> + See include/dt-bindings/phy/phy-qcom-qmp.h
>> +
>> + "#phy-cells":
>> + const: 1
>> + description:
>> + See include/dt-bindings/phy/phy-qcom-qmp.h
>> +
>> + qcom,tcsr-reg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to TCSR hardware block
>> + - description: offset of the VLS CLAMP register
>> + - items:
>> + - description: phandle to TCSR hardware block
>> + - description: offset of the DP PHY mode register
>> + description: Clamp and PHY mode register present in the TCSR
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - vdda-phy-supply
>> + - vdda-pll-supply
>> + - "#clock-cells"
>> + - "#phy-cells"
>> + - qcom,tcsr-reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> +
>> + phy@88e8000 {
>> + compatible = "qcom,qcs615-qmp-usb3-dp-phy";
>> + reg = <0x88e8000 0x2000>;
>> +
>> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
>> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
>> + clock-names = "cfg_ahb",
>> + "ref";
>> +
>> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
>> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
>> + reset-names = "phy_phy",
>> + "dp_phy";
>> +
>> + vdda-phy-supply = <&vreg_l11a>;
>> + vdda-pll-supply = <&vreg_l5a>;
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <1>;
>> +
>> + qcom,tcsr-reg = <&tcsr 0xbff0>,
>> + <&tcsr 0xb24c>;
>> + };
>>
>> --
>> 2.34.1
>>
On Fri, Aug 22, 2025 at 09:22:30AM -0500, Rob Herring wrote: > On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote: > > Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY > > on QCS615 Platform. This PHY supports both USB3 and DP functionality > > over USB-C, with PHY mode switching capability. It does not support > > combo mode. > > > > Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> > > --- > > .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++ > > 1 file changed, 108 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml > > + > > + resets: > > + maxItems: 2 > > + > > + reset-names: > > + items: > > + - const: phy_phy > > phy_phy? Yes, see other Qualcomm USB PHYs. And unfortunately we can not use just 'phy' here. Once this lands I plan to push corresponding changes for several other USBC PHYs (described in qcom,msm8998-qmp-usb3-phy.yaml) and those will have both "phy" and "phy_phy" resets. > > > + - const: dp_phy > > + -- With best wishes Dmitry
On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote:
> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
> on QCS615 Platform. This PHY supports both USB3 and DP functionality
> over USB-C, with PHY mode switching capability. It does not support
> combo mode.
>
> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
> ---
> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
> +
> +maintainers:
> + - Vinod Koul <vkoul@kernel.org>
> +
> +description:
> + The QMP PHY controller supports physical layer functionality for both
> + USB3 and DisplayPort over USB-C. While it enables mode switching
> + between USB3 and DisplayPort, but does not support combo mode.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qcs615-qmp-usb3-dp-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2
Missing GCC_USB2_SEC_PHY_AUX_CLK and GCC_USB2_SEC_PHY_PIPE_CLK
> +
> + clock-names:
> + items:
> + - const: cfg_ahb
> + - const: ref
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: phy_phy
> + - const: dp_phy
> +
> + vdda-phy-supply: true
> +
> + vdda-pll-supply: true
> +
> + "#clock-cells":
> + const: 1
> + description:
> + See include/dt-bindings/phy/phy-qcom-qmp.h
> +
> + "#phy-cells":
> + const: 1
> + description:
> + See include/dt-bindings/phy/phy-qcom-qmp.h
> +
> + qcom,tcsr-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to TCSR hardware block
> + - description: offset of the VLS CLAMP register
> + - items:
> + - description: phandle to TCSR hardware block
> + - description: offset of the DP PHY mode register
> + description: Clamp and PHY mode register present in the TCSR
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> + - "#clock-cells"
> + - "#phy-cells"
> + - qcom,tcsr-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + phy@88e8000 {
> + compatible = "qcom,qcs615-qmp-usb3-dp-phy";
> + reg = <0x88e8000 0x2000>;
> +
> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
> + reset-names = "phy_phy",
> + "dp_phy";
> +
> + vdda-phy-supply = <&vreg_l11a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + qcom,tcsr-reg = <&tcsr 0xbff0>,
> + <&tcsr 0xb24c>;
> + };
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 8/20/2025 7:37 PM, Dmitry Baryshkov wrote:
> On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote:
>> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
>> on QCS615 Platform. This PHY supports both USB3 and DP functionality
>> over USB-C, with PHY mode switching capability. It does not support
>> combo mode.
>>
>> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
>> ---
>> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
>> 1 file changed, 108 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
>> +
>> +maintainers:
>> + - Vinod Koul <vkoul@kernel.org>
>> +
>> +description:
>> + The QMP PHY controller supports physical layer functionality for both
>> + USB3 and DisplayPort over USB-C. While it enables mode switching
>> + between USB3 and DisplayPort, but does not support combo mode.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,qcs615-qmp-usb3-dp-phy
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 2
> Missing GCC_USB2_SEC_PHY_AUX_CLK and GCC_USB2_SEC_PHY_PIPE_CLK
Ok, will fix in next patch.
>> +
>> + clock-names:
>> + items:
>> + - const: cfg_ahb
>> + - const: ref
>> +
>> + resets:
>> + maxItems: 2
>> +
>> + reset-names:
>> + items:
>> + - const: phy_phy
>> + - const: dp_phy
>> +
>> + vdda-phy-supply: true
>> +
>> + vdda-pll-supply: true
>> +
>> + "#clock-cells":
>> + const: 1
>> + description:
>> + See include/dt-bindings/phy/phy-qcom-qmp.h
>> +
>> + "#phy-cells":
>> + const: 1
>> + description:
>> + See include/dt-bindings/phy/phy-qcom-qmp.h
>> +
>> + qcom,tcsr-reg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to TCSR hardware block
>> + - description: offset of the VLS CLAMP register
>> + - items:
>> + - description: phandle to TCSR hardware block
>> + - description: offset of the DP PHY mode register
>> + description: Clamp and PHY mode register present in the TCSR
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - vdda-phy-supply
>> + - vdda-pll-supply
>> + - "#clock-cells"
>> + - "#phy-cells"
>> + - qcom,tcsr-reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> +
>> + phy@88e8000 {
>> + compatible = "qcom,qcs615-qmp-usb3-dp-phy";
>> + reg = <0x88e8000 0x2000>;
>> +
>> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
>> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
>> + clock-names = "cfg_ahb",
>> + "ref";
>> +
>> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
>> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
>> + reset-names = "phy_phy",
>> + "dp_phy";
>> +
>> + vdda-phy-supply = <&vreg_l11a>;
>> + vdda-pll-supply = <&vreg_l5a>;
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <1>;
>> +
>> + qcom,tcsr-reg = <&tcsr 0xbff0>,
>> + <&tcsr 0xb24c>;
>> + };
>>
>> --
>> 2.34.1
>>
On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote:
> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
> on QCS615 Platform. This PHY supports both USB3 and DP functionality
> over USB-C, with PHY mode switching capability. It does not support
> combo mode.
>
> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
> ---
> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
> +
> +maintainers:
> + - Vinod Koul <vkoul@kernel.org>
> +
> +description:
> + The QMP PHY controller supports physical layer functionality for both
> + USB3 and DisplayPort over USB-C. While it enables mode switching
> + between USB3 and DisplayPort, but does not support combo mode.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qcs615-qmp-usb3-dp-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: cfg_ahb
> + - const: ref
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: phy_phy
> + - const: dp_phy
> +
> + vdda-phy-supply: true
> +
> + vdda-pll-supply: true
> +
> + "#clock-cells":
> + const: 1
> + description:
> + See include/dt-bindings/phy/phy-qcom-qmp.h
> +
> + "#phy-cells":
> + const: 1
> + description:
> + See include/dt-bindings/phy/phy-qcom-qmp.h
> +
> + qcom,tcsr-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to TCSR hardware block
> + - description: offset of the VLS CLAMP register
> + - items:
> + - description: phandle to TCSR hardware block
Why do we need two phandles?
> + - description: offset of the DP PHY mode register
s/DP PHY/PHY/
> + description: Clamp and PHY mode register present in the TCSR
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> + - "#clock-cells"
> + - "#phy-cells"
> + - qcom,tcsr-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + phy@88e8000 {
> + compatible = "qcom,qcs615-qmp-usb3-dp-phy";
> + reg = <0x88e8000 0x2000>;
> +
> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
> + reset-names = "phy_phy",
> + "dp_phy";
> +
> + vdda-phy-supply = <&vreg_l11a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + qcom,tcsr-reg = <&tcsr 0xbff0>,
> + <&tcsr 0xb24c>;
> + };
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 8/20/2025 6:09 PM, Dmitry Baryshkov wrote:
> On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote:
>> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
>> on QCS615 Platform. This PHY supports both USB3 and DP functionality
>> over USB-C, with PHY mode switching capability. It does not support
>> combo mode.
>>
>> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
>> ---
>> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++
>> 1 file changed, 108 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
>> +
>> +maintainers:
>> + - Vinod Koul <vkoul@kernel.org>
>> +
>> +description:
>> + The QMP PHY controller supports physical layer functionality for both
>> + USB3 and DisplayPort over USB-C. While it enables mode switching
>> + between USB3 and DisplayPort, but does not support combo mode.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,qcs615-qmp-usb3-dp-phy
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 2
>> +
>> + clock-names:
>> + items:
>> + - const: cfg_ahb
>> + - const: ref
>> +
>> + resets:
>> + maxItems: 2
>> +
>> + reset-names:
>> + items:
>> + - const: phy_phy
>> + - const: dp_phy
>> +
>> + vdda-phy-supply: true
>> +
>> + vdda-pll-supply: true
>> +
>> + "#clock-cells":
>> + const: 1
>> + description:
>> + See include/dt-bindings/phy/phy-qcom-qmp.h
>> +
>> + "#phy-cells":
>> + const: 1
>> + description:
>> + See include/dt-bindings/phy/phy-qcom-qmp.h
>> +
>> + qcom,tcsr-reg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to TCSR hardware block
>> + - description: offset of the VLS CLAMP register
>> + - items:
>> + - description: phandle to TCSR hardware block
> Why do we need two phandles?
Thanks for pointing that out. Will update to use a single phandle with multiple register offsets in the next patch.
>
>> + - description: offset of the DP PHY mode register
> s/DP PHY/PHY/
Ok. Will update in the next version.
>> + description: Clamp and PHY mode register present in the TCSR
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - vdda-phy-supply
>> + - vdda-pll-supply
>> + - "#clock-cells"
>> + - "#phy-cells"
>> + - qcom,tcsr-reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> +
>> + phy@88e8000 {
>> + compatible = "qcom,qcs615-qmp-usb3-dp-phy";
>> + reg = <0x88e8000 0x2000>;
>> +
>> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
>> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
>> + clock-names = "cfg_ahb",
>> + "ref";
>> +
>> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
>> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
>> + reset-names = "phy_phy",
>> + "dp_phy";
>> +
>> + vdda-phy-supply = <&vreg_l11a>;
>> + vdda-pll-supply = <&vreg_l5a>;
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <1>;
>> +
>> + qcom,tcsr-reg = <&tcsr 0xbff0>,
>> + <&tcsr 0xb24c>;
>> + };
>>
>> --
>> 2.34.1
>>
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