On Tuesday, August 19, 2025 9:16 PM Svyatoslav Ryhel wrote:
> Maximum width and height for Tegra20 and Tegra30 is determined by
> respective register field, rounded down to factor of 2, which is 8191U
> rounded down to 8190U.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/staging/media/tegra-video/tegra20.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/staging/media/tegra-video/tegra20.c
> b/drivers/staging/media/tegra-video/tegra20.c index
> 7b8f8f810b35..3e2d746638b6 100644
> --- a/drivers/staging/media/tegra-video/tegra20.c
> +++ b/drivers/staging/media/tegra-video/tegra20.c
> @@ -23,11 +23,10 @@
>
> #define TEGRA_VI_SYNCPT_WAIT_TIMEOUT
msecs_to_jiffies(200)
>
> -/* This are just good-sense numbers. The actual min/max is not documented.
> */ #define TEGRA20_MIN_WIDTH 32U
> +#define TEGRA20_MAX_WIDTH 8190U
> #define TEGRA20_MIN_HEIGHT 32U
> -#define TEGRA20_MAX_WIDTH 2048U
> -#define TEGRA20_MAX_HEIGHT 2048U
> +#define TEGRA20_MAX_HEIGHT 8190U
>
> /*
> --------------------------------------------------------------------------
> * Registers
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>