Add the Exynos ACPM clock driver. It provides support for clocks that
are controlled by firmware that implements the ACPM interface.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
drivers/clk/samsung/Kconfig | 10 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-acpm.c | 192 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 203 insertions(+)
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027af26272e30876a87ac293bd56dfa..fe05212d7dd882adde9cd5c656cd0d58d501c42f 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -95,6 +95,16 @@ config EXYNOS_CLKOUT
status of the certains clocks from SoC, but it could also be tied to
other devices as an input clock.
+config EXYNOS_ACPM_CLK
+ tristate "Clock driver controlled via ACPM interface"
+ depends on EXYNOS_ACPM_PROTOCOL || COMPILE_TEST
+ help
+ This driver provides support for clocks that are controlled by
+ firmware that implements the ACPM interface.
+
+ This driver uses the ACPM interface to interact with the firmware
+ providing all the clock controlls.
+
config TESLA_FSD_COMMON_CLK
bool "Tesla FSD clock controller support" if COMPILE_TEST
depends on COMMON_CLK_SAMSUNG
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b77fe288e4bb484c68d1ff497acc0b83d132ea03..04b63436b12f6f5169575d74f54b105e97bbb052 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos990.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
+obj-$(CONFIG_EXYNOS_ACPM_CLK) += clk-acpm.o
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c
new file mode 100644
index 0000000000000000000000000000000000000000..e3e648331ad54072876f52a63b11fe259a0b9be2
--- /dev/null
+++ b/drivers/clk/samsung/clk-acpm.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Samsung Exynos ACPM protocol based clock driver.
+ *
+ * Copyright 2025 Linaro Ltd.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/firmware/samsung/exynos-acpm-protocol.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include <dt-bindings/clock/google,gs101.h>
+
+struct acpm_clk {
+ u32 id;
+ struct clk_hw hw;
+ unsigned int acpm_chan_id;
+ const struct acpm_handle *handle;
+};
+
+#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw)
+
+struct acpm_clk_variant {
+ unsigned int id;
+ const char *name;
+};
+
+struct acpm_clk_match_data {
+ const struct acpm_clk_variant *clks;
+ unsigned int nr_clks;
+ unsigned int acpm_chan_id;
+};
+
+static unsigned long acpm_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct acpm_clk *clk = to_acpm_clk(hw);
+
+ return clk->handle->ops.dvfs_ops.get_rate(clk->handle,
+ clk->acpm_chan_id, clk->id, 0);
+}
+
+static long acpm_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ /*
+ * We can't figure out what rate it will be, so just return the
+ * rate back to the caller. acpm_clk_recalc_rate() will be called
+ * after the rate is set and we'll know what rate the clock is
+ * running at then.
+ */
+ return rate;
+}
+
+static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct acpm_clk *clk = to_acpm_clk(hw);
+
+ return clk->handle->ops.dvfs_ops.set_rate(clk->handle,
+ clk->acpm_chan_id, clk->id, rate);
+}
+
+static const struct clk_ops acpm_clk_ops = {
+ .recalc_rate = acpm_clk_recalc_rate,
+ .round_rate = acpm_clk_round_rate,
+ .set_rate = acpm_clk_set_rate,
+};
+
+static int __init acpm_clk_ops_init(struct device *dev, struct acpm_clk *aclk,
+ const char *name)
+{
+ struct clk_init_data init = {};
+
+ init.name = name;
+ init.ops = &acpm_clk_ops;
+ aclk->hw.init = &init;
+
+ return devm_clk_hw_register(dev, &aclk->hw);
+}
+
+static int __init acpm_clk_probe(struct platform_device *pdev)
+{
+ const struct acpm_clk_match_data *match_data;
+ const struct acpm_handle *acpm_handle;
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **hws;
+ struct device *dev = &pdev->dev;
+ struct acpm_clk *aclks;
+ unsigned int acpm_chan_id;
+ int i, err, count;
+
+ acpm_handle = devm_acpm_get_by_node(dev, dev->parent->of_node);
+ if (IS_ERR(acpm_handle))
+ return dev_err_probe(dev, PTR_ERR(acpm_handle),
+ "Failed to get acpm handle.\n");
+
+ match_data = of_device_get_match_data(dev);
+ if (!match_data)
+ return dev_err_probe(dev, -EINVAL,
+ "Failed to get match data.\n");
+
+ count = match_data->nr_clks;
+ acpm_chan_id = match_data->acpm_chan_id;
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ clk_data->num = count;
+ hws = clk_data->hws;
+
+ aclks = devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL);
+ if (!aclks)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ const struct acpm_clk_variant *variant = &match_data->clks[i];
+ struct acpm_clk *aclk = &aclks[i];
+
+ hws[i] = &aclk->hw;
+
+ aclk->id = variant->id;
+ aclk->handle = acpm_handle;
+ aclk->acpm_chan_id = acpm_chan_id;
+
+ err = acpm_clk_ops_init(dev, aclk, variant->name);
+ if (err)
+ return dev_err_probe(dev, err,
+ "Failed to register clock.\n");
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ clk_data);
+}
+
+#define ACPM_CLK(_id, cname) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ }
+
+static const struct acpm_clk_variant gs101_acpm_clks[] __initconst = {
+ ACPM_CLK(CLK_ACPM_DVFS_MIF, "mif"),
+ ACPM_CLK(CLK_ACPM_DVFS_INT, "int"),
+ ACPM_CLK(CLK_ACPM_DVFS_CPUCL0, "cpucl0"),
+ ACPM_CLK(CLK_ACPM_DVFS_CPUCL1, "cpucl1"),
+ ACPM_CLK(CLK_ACPM_DVFS_CPUCL2, "cpucl2"),
+ ACPM_CLK(CLK_ACPM_DVFS_G3D, "g3d"),
+ ACPM_CLK(CLK_ACPM_DVFS_G3DL2, "g3dl2"),
+ ACPM_CLK(CLK_ACPM_DVFS_TPU, "tpu"),
+ ACPM_CLK(CLK_ACPM_DVFS_INTCAM, "intcam"),
+ ACPM_CLK(CLK_ACPM_DVFS_TNR, "tnr"),
+ ACPM_CLK(CLK_ACPM_DVFS_CAM, "cam"),
+ ACPM_CLK(CLK_ACPM_DVFS_MFC, "mfc"),
+ ACPM_CLK(CLK_ACPM_DVFS_DISP, "disp"),
+ ACPM_CLK(CLK_ACPM_DVFS_BO, "b0"),
+};
+
+static const struct acpm_clk_match_data acpm_clk_gs101 __initconst = {
+ .clks = gs101_acpm_clks,
+ .nr_clks = ARRAY_SIZE(gs101_acpm_clks),
+ .acpm_chan_id = 0,
+};
+
+static const struct of_device_id acpm_clk_ids[] __initconst = {
+ {
+ .compatible = "google,gs101-acpm-dvfs-clocks",
+ .data = &acpm_clk_gs101,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, acpm_clk_ids);
+
+static struct platform_driver acpm_clk_driver __refdata = {
+ .driver = {
+ .name = "acpm-clocks",
+ .of_match_table = acpm_clk_ids,
+ },
+ .probe = acpm_clk_probe,
+};
+module_platform_driver(acpm_clk_driver);
+
+MODULE_AUTHOR("Tudor Ambarus <tudor.ambarus@linaro.org>");
+MODULE_DESCRIPTION("Samsung Exynos ACPM clock driver");
+MODULE_LICENSE("GPL");
--
2.51.0.rc1.167.g924127e9c0-googOn 19/08/2025 13:45, Tudor Ambarus wrote:
> +
> +static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct acpm_clk *clk = to_acpm_clk(hw);
> +
> + return clk->handle->ops.dvfs_ops.set_rate(clk->handle,
> + clk->acpm_chan_id, clk->id, rate);
> +}
> +
> +static const struct clk_ops acpm_clk_ops = {
> + .recalc_rate = acpm_clk_recalc_rate,
> + .round_rate = acpm_clk_round_rate,
This should be determine_rate. Check recent patchset from Brian Masney.
I applied the samsung bits from it to samsung soc tree.
...
> +
> +static int __init acpm_clk_probe(struct platform_device *pdev)
module probe for sure should not be __init.
> +{
> + const struct acpm_clk_match_data *match_data;
> + const struct acpm_handle *acpm_handle;
> + struct clk_hw_onecell_data *clk_data;
> + struct clk_hw **hws;
> + struct device *dev = &pdev->dev;
> + struct acpm_clk *aclks;
> + unsigned int acpm_chan_id;
> + int i, err, count;
> +
> + acpm_handle = devm_acpm_get_by_node(dev, dev->parent->of_node);
> + if (IS_ERR(acpm_handle))
> + return dev_err_probe(dev, PTR_ERR(acpm_handle),
> + "Failed to get acpm handle.\n");
> +
> + match_data = of_device_get_match_data(dev);
> + if (!match_data)
> + return dev_err_probe(dev, -EINVAL,
> + "Failed to get match data.\n");
> +
> + count = match_data->nr_clks;
> + acpm_chan_id = match_data->acpm_chan_id;
> +
> + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
> + GFP_KERNEL);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + clk_data->num = count;
> + hws = clk_data->hws;
> +
> + aclks = devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL);
> + if (!aclks)
> + return -ENOMEM;
> +
> + for (i = 0; i < count; i++) {
> + const struct acpm_clk_variant *variant = &match_data->clks[i];
> + struct acpm_clk *aclk = &aclks[i];
> +
> + hws[i] = &aclk->hw;
> +
> + aclk->id = variant->id;
> + aclk->handle = acpm_handle;
> + aclk->acpm_chan_id = acpm_chan_id;
> +
> + err = acpm_clk_ops_init(dev, aclk, variant->name);
> + if (err)
> + return dev_err_probe(dev, err,
> + "Failed to register clock.\n");
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + clk_data);
> +}
> +
> +#define ACPM_CLK(_id, cname) \
> + { \
> + .id = _id, \
> + .name = cname, \
> + }
> +
> +static const struct acpm_clk_variant gs101_acpm_clks[] __initconst = {
This goes to top of the file, after struct declarations.
> + ACPM_CLK(CLK_ACPM_DVFS_MIF, "mif"),
> + ACPM_CLK(CLK_ACPM_DVFS_INT, "int"),
> + ACPM_CLK(CLK_ACPM_DVFS_CPUCL0, "cpucl0"),
> + ACPM_CLK(CLK_ACPM_DVFS_CPUCL1, "cpucl1"),
> + ACPM_CLK(CLK_ACPM_DVFS_CPUCL2, "cpucl2"),
> + ACPM_CLK(CLK_ACPM_DVFS_G3D, "g3d"),
> + ACPM_CLK(CLK_ACPM_DVFS_G3DL2, "g3dl2"),
> + ACPM_CLK(CLK_ACPM_DVFS_TPU, "tpu"),
> + ACPM_CLK(CLK_ACPM_DVFS_INTCAM, "intcam"),
> + ACPM_CLK(CLK_ACPM_DVFS_TNR, "tnr"),
> + ACPM_CLK(CLK_ACPM_DVFS_CAM, "cam"),
> + ACPM_CLK(CLK_ACPM_DVFS_MFC, "mfc"),
> + ACPM_CLK(CLK_ACPM_DVFS_DISP, "disp"),
> + ACPM_CLK(CLK_ACPM_DVFS_BO, "b0"),
> +};
> +
> +static const struct acpm_clk_match_data acpm_clk_gs101 __initconst = {
Are you going to have more of such clk_match_data? More variants?
> + .clks = gs101_acpm_clks,
> + .nr_clks = ARRAY_SIZE(gs101_acpm_clks),
> + .acpm_chan_id = 0,
> +};
> +
> +static const struct of_device_id acpm_clk_ids[] __initconst = {
> + {
> + .compatible = "google,gs101-acpm-dvfs-clocks",
> + .data = &acpm_clk_gs101,
> + },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, acpm_clk_ids);
> +
> +static struct platform_driver acpm_clk_driver __refdata = {
__refdata feels wrong here. There is a long standing issue with Samsung
clock drivers - I sent a patchset for that but it did failed testing.
But your code is even simpler - no CLK_OFDECLARE - so why is this refdata?
Best regards,
Krzysztof
On 8/24/25 6:10 PM, Krzysztof Kozlowski wrote:
> On 19/08/2025 13:45, Tudor Ambarus wrote:
>> +
>> +static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct acpm_clk *clk = to_acpm_clk(hw);
>> +
>> + return clk->handle->ops.dvfs_ops.set_rate(clk->handle,
>> + clk->acpm_chan_id, clk->id, rate);
>> +}
>> +
>> +static const struct clk_ops acpm_clk_ops = {
>> + .recalc_rate = acpm_clk_recalc_rate,
>> + .round_rate = acpm_clk_round_rate,
>
> This should be determine_rate. Check recent patchset from Brian Masney.
> I applied the samsung bits from it to samsung soc tree.
Will do.
>
> ...
>
>> +
>> +static int __init acpm_clk_probe(struct platform_device *pdev)
>
> module probe for sure should not be __init.
Ah, indeed, both __init and __refdata are wrong here, my appologies.
I assume they came from the time I considered the driver only needed
at boot time. Will drop them.
>
>> +{
>> + const struct acpm_clk_match_data *match_data;
>> + const struct acpm_handle *acpm_handle;
>> + struct clk_hw_onecell_data *clk_data;
>> + struct clk_hw **hws;
>> + struct device *dev = &pdev->dev;
>> + struct acpm_clk *aclks;
>> + unsigned int acpm_chan_id;
>> + int i, err, count;
>> +
>> + acpm_handle = devm_acpm_get_by_node(dev, dev->parent->of_node);
>> + if (IS_ERR(acpm_handle))
>> + return dev_err_probe(dev, PTR_ERR(acpm_handle),
>> + "Failed to get acpm handle.\n");
>> +
>> + match_data = of_device_get_match_data(dev);
>> + if (!match_data)
>> + return dev_err_probe(dev, -EINVAL,
>> + "Failed to get match data.\n");
>> +
>> + count = match_data->nr_clks;
>> + acpm_chan_id = match_data->acpm_chan_id;
>> +
>> + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
>> + GFP_KERNEL);
>> + if (!clk_data)
>> + return -ENOMEM;
>> +
>> + clk_data->num = count;
>> + hws = clk_data->hws;
>> +
>> + aclks = devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL);
>> + if (!aclks)
>> + return -ENOMEM;
>> +
>> + for (i = 0; i < count; i++) {
>> + const struct acpm_clk_variant *variant = &match_data->clks[i];
>> + struct acpm_clk *aclk = &aclks[i];
>> +
>> + hws[i] = &aclk->hw;
>> +
>> + aclk->id = variant->id;
>> + aclk->handle = acpm_handle;
>> + aclk->acpm_chan_id = acpm_chan_id;
>> +
>> + err = acpm_clk_ops_init(dev, aclk, variant->name);
>> + if (err)
>> + return dev_err_probe(dev, err,
>> + "Failed to register clock.\n");
>> + }
>> +
>> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> + clk_data);
>> +}
>> +
>> +#define ACPM_CLK(_id, cname) \
>> + { \
>> + .id = _id, \
>> + .name = cname, \
>> + }
>> +
>> +static const struct acpm_clk_variant gs101_acpm_clks[] __initconst = {
>
> This goes to top of the file, after struct declarations.
Okay, will do.
>
>> + ACPM_CLK(CLK_ACPM_DVFS_MIF, "mif"),
>> + ACPM_CLK(CLK_ACPM_DVFS_INT, "int"),
>> + ACPM_CLK(CLK_ACPM_DVFS_CPUCL0, "cpucl0"),
>> + ACPM_CLK(CLK_ACPM_DVFS_CPUCL1, "cpucl1"),
>> + ACPM_CLK(CLK_ACPM_DVFS_CPUCL2, "cpucl2"),
>> + ACPM_CLK(CLK_ACPM_DVFS_G3D, "g3d"),
>> + ACPM_CLK(CLK_ACPM_DVFS_G3DL2, "g3dl2"),
>> + ACPM_CLK(CLK_ACPM_DVFS_TPU, "tpu"),
>> + ACPM_CLK(CLK_ACPM_DVFS_INTCAM, "intcam"),
>> + ACPM_CLK(CLK_ACPM_DVFS_TNR, "tnr"),
>> + ACPM_CLK(CLK_ACPM_DVFS_CAM, "cam"),
>> + ACPM_CLK(CLK_ACPM_DVFS_MFC, "mfc"),
>> + ACPM_CLK(CLK_ACPM_DVFS_DISP, "disp"),
>> + ACPM_CLK(CLK_ACPM_DVFS_BO, "b0"),
>> +};
>> +
>> +static const struct acpm_clk_match_data acpm_clk_gs101 __initconst = {
>
> Are you going to have more of such clk_match_data? More variants?
I see downstream that gs101 and gs201 have the same clock IDs, clock names
and acpm_chan_id. But I can't tell about others. I assume it's safer to
assume there will be other variants.
Anyway, I'll pass this as platform data, if I understood correctly.
Thanks,
ta
>
>> + .clks = gs101_acpm_clks,
>> + .nr_clks = ARRAY_SIZE(gs101_acpm_clks),
>> + .acpm_chan_id = 0,
>> +};
>> +
Hi Tudor,
On Tue, Aug 19, 2025 at 11:45:38AM +0000, Tudor Ambarus wrote:
> +static long acpm_clk_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *parent_rate)
> +{
> + /*
> + * We can't figure out what rate it will be, so just return the
> + * rate back to the caller. acpm_clk_recalc_rate() will be called
> + * after the rate is set and we'll know what rate the clock is
> + * running at then.
> + */
> + return rate;
> +}
...
> +
> +static const struct clk_ops acpm_clk_ops = {
> + .recalc_rate = acpm_clk_recalc_rate,
> + .round_rate = acpm_clk_round_rate,
> + .set_rate = acpm_clk_set_rate,
> +};
The round_rate clk op is deprecated. Please convert this over to use
determine_rate.
Brian
On 8/21/25 7:34 PM, Brian Masney wrote:
> Hi Tudor,
Hi, Brian,
>
> On Tue, Aug 19, 2025 at 11:45:38AM +0000, Tudor Ambarus wrote:
>> +static long acpm_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *parent_rate)
>> +{
>> + /*
>> + * We can't figure out what rate it will be, so just return the
>> + * rate back to the caller. acpm_clk_recalc_rate() will be called
>> + * after the rate is set and we'll know what rate the clock is
>> + * running at then.
>> + */
>> + return rate;
>> +}
>
> ...
>
>> +
>> +static const struct clk_ops acpm_clk_ops = {
>> + .recalc_rate = acpm_clk_recalc_rate,
>> + .round_rate = acpm_clk_round_rate,
>> + .set_rate = acpm_clk_set_rate,
>> +};
>
> The round_rate clk op is deprecated. Please convert this over to use
> determine_rate.
I can do that, sure. Shall I also update the kdoc for round_rate(), mark it
as deprecated and add your Suggested-by tag? It would help other newcomers.
Thanks,
ta
Hi Tudor,
On Fri, Aug 22, 2025 at 09:14:03AM +0100, Tudor Ambarus wrote:
> On 8/21/25 7:34 PM, Brian Masney wrote:
> > On Tue, Aug 19, 2025 at 11:45:38AM +0000, Tudor Ambarus wrote:
> >> +static long acpm_clk_round_rate(struct clk_hw *hw, unsigned long rate,
> >> + unsigned long *parent_rate)
> >> +{
> >> + /*
> >> + * We can't figure out what rate it will be, so just return the
> >> + * rate back to the caller. acpm_clk_recalc_rate() will be called
> >> + * after the rate is set and we'll know what rate the clock is
> >> + * running at then.
> >> + */
> >> + return rate;
> >> +}
> >
> > ...
> >
> >> +
> >> +static const struct clk_ops acpm_clk_ops = {
> >> + .recalc_rate = acpm_clk_recalc_rate,
> >> + .round_rate = acpm_clk_round_rate,
> >> + .set_rate = acpm_clk_set_rate,
> >> +};
> >
> > The round_rate clk op is deprecated. Please convert this over to use
> > determine_rate.
>
> I can do that, sure. Shall I also update the kdoc for round_rate(), mark it
> as deprecated and add your Suggested-by tag? It would help other newcomers.
I am working to remove round_rate from the clk core and the various
drivers. Your driver just needs to be updated similar to this:
https://lore.kernel.org/all/20250710-clk-imx-round-rate-v1-10-5726f98e6d8d@redhat.com/
Brian
On 8/22/25 11:23 AM, Brian Masney wrote:
> Hi Tudor,
>
> On Fri, Aug 22, 2025 at 09:14:03AM +0100, Tudor Ambarus wrote:
>> On 8/21/25 7:34 PM, Brian Masney wrote:
>>> On Tue, Aug 19, 2025 at 11:45:38AM +0000, Tudor Ambarus wrote:
>>>> +static long acpm_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>>>> + unsigned long *parent_rate)
>>>> +{
>>>> + /*
>>>> + * We can't figure out what rate it will be, so just return the
>>>> + * rate back to the caller. acpm_clk_recalc_rate() will be called
>>>> + * after the rate is set and we'll know what rate the clock is
>>>> + * running at then.
>>>> + */
>>>> + return rate;
>>>> +}
>>>
>>> ...
>>>
>>>> +
>>>> +static const struct clk_ops acpm_clk_ops = {
>>>> + .recalc_rate = acpm_clk_recalc_rate,
>>>> + .round_rate = acpm_clk_round_rate,
>>>> + .set_rate = acpm_clk_set_rate,
>>>> +};
>>>
>>> The round_rate clk op is deprecated. Please convert this over to use
>>> determine_rate.
>>
>> I can do that, sure. Shall I also update the kdoc for round_rate(), mark it
>> as deprecated and add your Suggested-by tag? It would help other newcomers.
>
> I am working to remove round_rate from the clk core and the various
ah, great. Thanks for the pointer!
> drivers. Your driver just needs to be updated similar to this:
>
> https://lore.kernel.org/all/20250710-clk-imx-round-rate-v1-10-5726f98e6d8d@redhat.com/
>
> Brian
>
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