From: Irving-ch Lin <irving-ch.lin@mediatek.com>

Add the new binding documentation for power controller
on MediaTek MT8189.

Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.com>
---
 .../mediatek,mt8189-power-controller.yaml     | 94 +++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml

diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
new file mode 100644
index 000000000000..1bf8f94858c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/mediatek,mt8189-power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Power Domains Controller for MT8189
+
+maintainers:
+  - Qiqi Wang <qiqi.wang@mediatek.com>
+
+description: |
+  MediaTek processors include support for multiple power domains which can be
+  powered up/down by software based on different application scenes to save power.
+
+  IP cores belonging to a power domain should contain a 'power-domains'
+  property that is a phandle for SCPSYS node representing the domain.
+
+properties:
+  $nodename:
+    pattern: '^power-controller(@[0-9a-f]+)?$'
+
+  compatible:
+    enum:
+      - mediatek,mt8189-scpsys
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    description: physical base address and size of the power-controller's register area.
+
+  infra-infracfg-ao-reg-bus:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the device containing the infracfg register range.
+
+  emicfg-ao-mem:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the device containing the emicfg register range.
+
+  vlpcfg-reg-bus:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the device containing the vlpcfg (very low power config) register range.
+
+  clocks:
+    description: |
+      A number of phandles to clocks that need to be enabled during domain
+      power-up sequencing.
+
+  clock-names:
+    description: |
+      List of names of clocks, in order to match the power-up sequencing
+      for each power domain we need to group the clocks by name. BASIC
+      clocks need to be enabled before enabling the corresponding power
+      domain, and should not have a '-' in their name (i.e mm, mfg, venc).
+      SUSBYS clocks need to be enabled before releasing the bus protection,
+      and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
+
+      In order to follow properly the power-up sequencing, the clocks must
+      be specified by order, adding first the BASIC clocks followed by the
+      SUSBSYS clocks.
+
+  domain-supply:
+    description: domain regulator supply.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8189-clk.h>
+    #include <dt-bindings/power/mt8189-power.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        scpsys: power-controller@1c001000 {
+            compatible = "mediatek,mt8189-scpsys";
+            reg = <0 0x1c001000 0 0x1000>;
+            #power-domain-cells = <1>;
+            infra-infracfg-ao-reg-bus = <&infracfg_ao_clk>;
+            emicfg-ao-mem = <&emicfg_ao_mem_clk>;
+            vlpcfg-reg-bus = <&vlpcfg_reg_bus_clk>;
+            clocks = /* MFG */
+                <&topckgen_clk CLK_TOP_MFG_REF_SEL>,
+                <&apmixedsys_clk CLK_APMIXED_MFGPLL>;
+            clock-names = "mfg", "mfg_top";
+            mfg0-supply = <&mt6359_vproc1_buck_reg>;
+            mfg1-supply = <&mt6359_vsram_proc1_ldo_reg>;
+        };
+    };
-- 
2.45.2

On 18/08/2025 13:57, irving.ch.lin wrote:
> From: Irving-ch Lin <irving-ch.lin@mediatek.com>
> 
> Add the new binding documentation for power controller
> on MediaTek MT8189.
> 
> Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.com>
> ---
>  .../mediatek,mt8189-power-controller.yaml     | 94 +++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> 
> diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> new file mode 100644
> index 000000000000..1bf8f94858c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/power/mediatek,mt8189-power-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Power Domains Controller for MT8189
> +
> +maintainers:
> +  - Qiqi Wang <qiqi.wang@mediatek.com>
> +
> +description: |
> +  MediaTek processors include support for multiple power domains which can be
> +  powered up/down by software based on different application scenes to save power.
> +
> +  IP cores belonging to a power domain should contain a 'power-domains'
> +  property that is a phandle for SCPSYS node representing the domain.
> +
> +properties:
> +  $nodename:
> +    pattern: '^power-controller(@[0-9a-f]+)?$'

Drop. Reg is not optional.

> +
> +  compatible:
> +    enum:
> +      - mediatek,mt8189-scpsys
> +

reg goes here.

> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    description: physical base address and size of the power-controller's register area.

No. Don't use AI tools... Look how this is written based on other bindings.

> +
> +  infra-infracfg-ao-reg-bus:

Follow established practice... You do not get common properties.

> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: phandle to the device containing the infracfg register range.

Also do not say what is obvious from property name, but explain the purpose.


> +
> +  emicfg-ao-mem:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: phandle to the device containing the emicfg register range.
> +
> +  vlpcfg-reg-bus:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: phandle to the device containing the vlpcfg (very low power config) register range.
> +
> +  clocks:
> +    description: |
> +      A number of phandles to clocks that need to be enabled during domain
> +      power-up sequencing.
> +
> +  clock-names:
> +    description: |
> +      List of names of clocks, in order to match the power-up sequencing
> +      for each power domain we need to group the clocks by name. BASIC
> +      clocks need to be enabled before enabling the corresponding power
> +      domain, and should not have a '-' in their name (i.e mm, mfg, venc).
> +      SUSBYS clocks need to be enabled before releasing the bus protection,
> +      and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
> +
> +      In order to follow properly the power-up sequencing, the clocks must
> +      be specified by order, adding first the BASIC clocks followed by the
> +      SUSBSYS clocks.
> +
> +  domain-supply:
> +    description: domain regulator supply.
> +
> +required:
> +  - compatible
> +  - reg
Incomplete. Devices cannot work without power and many other things.

Sorry, but this binding is very poor and I feel like you did not put
enough of effort to write correct one. You are not independent
contributor, but do it as part of Mediatek, so I do not understand why
in Mediatek you cannot do basic in-house review.


Best regards,
Krzysztof

On Mon, 18 Aug 2025 19:57:30 +0800, irving.ch.lin wrote:
> From: Irving-ch Lin <irving-ch.lin@mediatek.com>
> 
> Add the new binding documentation for power controller
> on MediaTek MT8189.
> 
> Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.com>
> ---
>  .../mediatek,mt8189-power-controller.yaml     | 94 +++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.example.dts:18:18: fatal error: dt-bindings/clock/mt8189-clk.h: No such file or directory
   18 |         #include <dt-bindings/clock/mt8189-clk.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:132: Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1525: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250818115754.1067154-3-irving-ch.lin@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.