[v3] x86/cpu/topology: Work around the nuances of virtualization on AMD/Hygon

[PATCH v3 0/4] x86/cpu/topology: Work around the nuances of virtualization on AMD/Hygon

Posted by K Prateek Nayak 1 month, 2 weeks ago

When running an AMD guest on QEMU with > 255 cores, the following FW_BUG
was noticed with recent kernels:

[Firmware Bug]: CPU 512: APIC ID mismatch. CPUID: 0x0000 APIC: 0x0200

Naveen, Sairaj debugged the cause to commit c749ce393b8f ("x86/cpu: Use
common topology code for AMD") where, after the rework, the initial
APICID was set using the CPUID leaf 0x8000001e EAX[31:0] as opposed to
the value from CPUID leaf 0xb EDX[31:0] previously.

This led us down a rabbit hole of XTOPOEXT vs TOPOEXT support, preferred
order of their parsing, and QEMU nuances like [1] where QEMU 0's out the
CPUID leaf 0x8000001e on CPUs where Core ID crosses 255 fearing a
Core ID collision in the 8 bit field which leads to the reported FW_BUG.

Following were major observations during the debug which the two
patches address respectively:

1. The support for CPUID leaf 0xb is independent of the TOPOEXT feature
and is rather linked to the x2APIC enablement. On baremetal, this has
not been a problem since TOPOEXT support (Fam 0x15 and above)
predates the support for CPUID leaf 0xb (Fam 0x17[Zen2] and above)
however, in virtualized environment, the support for x2APIC can be
enabled independent of topoext where QEMU expects the guest to parse
the topology and the APICID from CPUID leaf 0xb.

2. Since CPUID leaf 0x8000001e cannot represent Core ID without
collision for guests with > 255 cores, and QEMU 0's out the entire
leaf when Core ID crosses 255. Prefer initial APIC read from the
XTOPOEXT leaf before falling back to the APICID from 0x8000001e
which is still better than 8-bit APICID from leaf 0x1 EBX[31:24].

More details are enclosed in the commit logs.

Ideally, these changes should not affect baremetal AMD/Hygon platforms
as they have supported TOPOEXT long before the support for CPUID leaf
0xb and the extended CPUID leaf 0x80000026 (famous last words).

Patch 1 and 4 is yak shaving to explicitly define a raw MSR value used
in the topology parsing bits and simplify the flow around "has_topoext"
when the same can be discovered using X86_FEATURE_XTOPOLOGY.

This series has been tested on baremetal Zen1 (contains topoext but not
0xb leaf), Zen3 (contains both topoext and 0xb leaf), and Zen4 (contains
topoext, 0xb leaf, and 0x80000026 leaf) servers with no changes
observed in "/sys/kernel/debug/x86/topo/" directory.

The series was also tested on 255 and 512 vCPU (each vCPU is an
individual core from QEMU topology being passed) EPYC-Genoa guest with
and without x2apic and topoext enabled and this series solves the FW_BUG
seen on guest with > 255 VCPUs. No changes observed in
"/sys/kernel/debug/x86/topo/" for all other cases without warning.
0xb leaf is provided unconditionally on these guests (with or without
topoext, even with x2apic disabled on guests with <= 255 vCPU).

In all the cases initial_apicid matched the apicid in
"/sys/kernel/debug/x86/topo/" after applying this series.

Relevant bits of QEMU cmdline used during testing are as follows:

qemu-system-x86_64 \
-enable-kvm -m 32G -smp cpus=512,cores=512 \
-cpu EPYC-Genoa,x2apic=on,kvm-msi-ext-dest-id=on,+kvm-pv-unhalt,kvm-pv-tlb-flush,kvm-pv-ipi,kvm-pv-sched-yield,[-topoext] \
-machine q35,kernel_irqchip=split \
-global kvm-pit.lost_tick_policy=discard
...

References:

[1] https://github.com/qemu/qemu/commit/35ac5dfbcaa4b

Series is based on tip:x86/cpu at commit 65f55a301766 ("x86/CPU/AMD: Add
CPUID faulting support")
---
Changelog v2..v3:

o Patch 1 was added to the series.
o Use cpu_feature_enabled() in Patch 3.
o Rebased on top of tip:x86/cpu.

v2: https://lore.kernel.org/lkml/20250725110622.59743-1-kprateek.nayak@amd.com/

Changelog v1..v2:

o Collected tags from Naveen. (Thank you for testing!)
o Rebased the series on tip:x86/cpu.
o Swapped Patch 1 and Patch 2 from v1.
o Merged the body of two if blocks in Patch 1 to allow for cleanup in
Patch 3.

v1: https://lore.kernel.org/lkml/20250612072921.15107-1-kprateek.nayak@amd.com/
---
K Prateek Nayak (4):
x86/msr-index: Define AMD64_CPUID_FN_EXT MSR
x86/cpu/topology: Use initial APICID from XTOPOEXT on AMD/HYGON
x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon
x86/cpu/topology: Check for X86_FEATURE_XTOPOLOGY instead of passing
has_topoext

arch/x86/include/asm/msr-index.h | 5 +++
arch/x86/kernel/cpu/topology_amd.c | 55 ++++++++++++++++--------------
2 files changed, 34 insertions(+), 26 deletions(-)

base-commit: 5bf2f5119b9e957f773a22f226974166b58cff32
--
2.34.1