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[PATCH 1/4] arm64/sysreg: Update TCR_EL1 register

Anshuman Khandual posted 4 patches 5 months, 3 weeks ago
[PATCH 1/4] arm64/sysreg: Update TCR_EL1 register
Posted by Anshuman Khandual 5 months, 3 weeks ago 
Update TCR_EL1 register fields as per latest ARM ARM DDI 0487 7.B and while
here drop an explicit sysreg definition SYS_TCR_EL1 from sysreg.h, which is
now redundant.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/sysreg.h |  2 --
 arch/arm64/tools/sysreg         | 52 ++++++++++++++++++++++++++++-----
 2 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d5b5f2ae1afa..ad5c901af229 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -281,8 +281,6 @@
 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
 
-#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
-
 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 696ab1f32a67..4bdae8bb11dc 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -4756,17 +4756,53 @@ Field   37      TBI0
 Field   36      AS
 Res0    35
 Field   34:32   IPS
-Field   31:30   TG1
-Field   29:28   SH1
-Field   27:26   ORGN1
-Field   25:24   IRGN1
+UnsignedEnum   31:30   TG1
+	0b01	16K
+	0b10	4K
+	0b11	64K
+EndEnum
+UnsignedEnum   29:28   SH1
+	0b00	NONE
+	0b10	OUTER
+	0b11	INNER
+EndEnum
+UnsignedEnum   27:26  ORGN1
+	0b00	NC
+	0b01	WBWA
+	0b10	WT
+	0b11	WBnWA
+EndEnum
+UnsignedEnum   25:24   IRGN1
+	0b00	NC
+	0b01	WBWA
+	0b10	WT
+	0b11	WBnWA
+EndEnum
 Field   23      EPD1
 Field   22      A1
 Field   21:16   T1SZ
-Field   15:14   TG0
-Field   13:12   SH0
-Field   11:10   ORGN0
-Field   9:8     IRGN0
+UnsignedEnum   15:14   TG0
+	0b00	4K
+	0b01	64K
+	0b10	16K
+EndEnum
+UnsignedEnum   13:12   SH0
+	0b00	NONE
+	0b10	OUTER
+	0b11	INNER
+EndEnum
+UnsignedEnum   11:10  ORGN0
+	0b00	NC
+	0b01	WBWA
+	0b10	WT
+	0b11	WBnWA
+EndEnum
+UnsignedEnum   9:8   IRGN0
+	0b00	NC
+	0b01	WBWA
+	0b10	WT
+	0b11	WBnWA
+EndEnum
 Field   7       EPD0
 Res0    6
 Field   5:0     T0SZ
-- 
2.25.1
Re: [PATCH 1/4] arm64/sysreg: Update TCR_EL1 register
Posted by Mark Rutland 5 months, 3 weeks ago 
On Mon, Aug 18, 2025 at 10:27:56AM +0530, Anshuman Khandual wrote:
> Update TCR_EL1 register fields as per latest ARM ARM DDI 0487 7.B and while
> here drop an explicit sysreg definition SYS_TCR_EL1 from sysreg.h, which is
> now redundant.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  arch/arm64/include/asm/sysreg.h |  2 --
>  arch/arm64/tools/sysreg         | 52 ++++++++++++++++++++++++++++-----
>  2 files changed, 44 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index d5b5f2ae1afa..ad5c901af229 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -281,8 +281,6 @@
>  #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
>  #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
>  
> -#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
> -
>  #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
>  #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
>  #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 696ab1f32a67..4bdae8bb11dc 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -4756,17 +4756,53 @@ Field   37      TBI0
>  Field   36      AS
>  Res0    35
>  Field   34:32   IPS
> -Field   31:30   TG1
> -Field   29:28   SH1
> -Field   27:26   ORGN1
> -Field   25:24   IRGN1
> +UnsignedEnum   31:30   TG1
> +	0b01	16K
> +	0b10	4K
> +	0b11	64K
> +EndEnum

This is clearly not an ordered set.

This should just use Enum, not UnsignedEnum.

Likewise for all the other cases below.

Mark.

> +UnsignedEnum   29:28   SH1
> +	0b00	NONE
> +	0b10	OUTER
> +	0b11	INNER
> +EndEnum
> +UnsignedEnum   27:26  ORGN1
> +	0b00	NC
> +	0b01	WBWA
> +	0b10	WT
> +	0b11	WBnWA
> +EndEnum
> +UnsignedEnum   25:24   IRGN1
> +	0b00	NC
> +	0b01	WBWA
> +	0b10	WT
> +	0b11	WBnWA
> +EndEnum
>  Field   23      EPD1
>  Field   22      A1
>  Field   21:16   T1SZ
> -Field   15:14   TG0
> -Field   13:12   SH0
> -Field   11:10   ORGN0
> -Field   9:8     IRGN0
> +UnsignedEnum   15:14   TG0
> +	0b00	4K
> +	0b01	64K
> +	0b10	16K
> +EndEnum
> +UnsignedEnum   13:12   SH0
> +	0b00	NONE
> +	0b10	OUTER
> +	0b11	INNER
> +EndEnum
> +UnsignedEnum   11:10  ORGN0
> +	0b00	NC
> +	0b01	WBWA
> +	0b10	WT
> +	0b11	WBnWA
> +EndEnum
> +UnsignedEnum   9:8   IRGN0
> +	0b00	NC
> +	0b01	WBWA
> +	0b10	WT
> +	0b11	WBnWA
> +EndEnum
>  Field   7       EPD0
>  Res0    6
>  Field   5:0     T0SZ
> -- 
> 2.25.1
> 
>
Re: [PATCH 1/4] arm64/sysreg: Update TCR_EL1 register
Posted by Anshuman Khandual 5 months, 3 weeks ago 

On 18/08/25 2:41 PM, Mark Rutland wrote:
> On Mon, Aug 18, 2025 at 10:27:56AM +0530, Anshuman Khandual wrote:
>> Update TCR_EL1 register fields as per latest ARM ARM DDI 0487 7.B and while
>> here drop an explicit sysreg definition SYS_TCR_EL1 from sysreg.h, which is
>> now redundant.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Brown <broonie@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/arm64/include/asm/sysreg.h |  2 --
>>  arch/arm64/tools/sysreg         | 52 ++++++++++++++++++++++++++++-----
>>  2 files changed, 44 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index d5b5f2ae1afa..ad5c901af229 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -281,8 +281,6 @@
>>  #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
>>  #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
>>  
>> -#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
>> -
>>  #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
>>  #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
>>  #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index 696ab1f32a67..4bdae8bb11dc 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -4756,17 +4756,53 @@ Field   37      TBI0
>>  Field   36      AS
>>  Res0    35
>>  Field   34:32   IPS
>> -Field   31:30   TG1
>> -Field   29:28   SH1
>> -Field   27:26   ORGN1
>> -Field   25:24   IRGN1
>> +UnsignedEnum   31:30   TG1
>> +	0b01	16K
>> +	0b10	4K
>> +	0b11	64K
>> +EndEnum
> 
> This is clearly not an ordered set.
> 
> This should just use Enum, not UnsignedEnum.
> 
> Likewise for all the other cases below.

Sure, will change.
> 
> Mark.
> 
>> +UnsignedEnum   29:28   SH1
>> +	0b00	NONE
>> +	0b10	OUTER
>> +	0b11	INNER
>> +EndEnum
>> +UnsignedEnum   27:26  ORGN1
>> +	0b00	NC
>> +	0b01	WBWA
>> +	0b10	WT
>> +	0b11	WBnWA
>> +EndEnum
>> +UnsignedEnum   25:24   IRGN1
>> +	0b00	NC
>> +	0b01	WBWA
>> +	0b10	WT
>> +	0b11	WBnWA
>> +EndEnum
>>  Field   23      EPD1
>>  Field   22      A1
>>  Field   21:16   T1SZ
>> -Field   15:14   TG0
>> -Field   13:12   SH0
>> -Field   11:10   ORGN0
>> -Field   9:8     IRGN0
>> +UnsignedEnum   15:14   TG0
>> +	0b00	4K
>> +	0b01	64K
>> +	0b10	16K
>> +EndEnum
>> +UnsignedEnum   13:12   SH0
>> +	0b00	NONE
>> +	0b10	OUTER
>> +	0b11	INNER
>> +EndEnum
>> +UnsignedEnum   11:10  ORGN0
>> +	0b00	NC
>> +	0b01	WBWA
>> +	0b10	WT
>> +	0b11	WBnWA
>> +EndEnum
>> +UnsignedEnum   9:8   IRGN0
>> +	0b00	NC
>> +	0b01	WBWA
>> +	0b10	WT
>> +	0b11	WBnWA
>> +EndEnum
>>  Field   7       EPD0
>>  Res0    6
>>  Field   5:0     T0SZ
>> -- 
>> 2.25.1
>>
>>

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