The Samsung HDMI/eDP Transmitter Combo PHY is capable of handling four
HDMI 2.1 Fixed Rate Link (FRL) lanes, while each lane can operate at
3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps.
This patchset extends the HDMI PHY configuration API to manage the FRL
mode and provides all the required HDMI driver changes to enable FRL in
addition to the already supported TMDS mode.
The series also contains a few driver fixes/improvements that are not
directly related, but are not deemed critical enough to warrant separate
submission.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Changes in v3:
- Reworked patch "phy: hdmi: Add HDMI 2.1 FRL configuration options"
according to Dmitry's feedback
* Updated commit message providing a brief description of FRL mode
* Kept PHY_MODE_HDMI in enum phy_mode and introduced enum
phy_mode_hdmi defining the TMDS and FRL submodes
- Updated "phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support"
* Implemented .set_mode() callback in rk_hdptx_phy_ops
* Introduced .mode member in struct rk_hdptx_hdmi_cfg and used it
instead of phy_get_mode() to verify PHY_MODE_HDMI_FRL
- Rebased series onto next-20250818
- Link to v2: https://lore.kernel.org/r/20250805-phy-hdptx-frl-v2-0-d118bd4b6e0b@collabora.com
Changes in v2:
- Added a couple of new patches:
* Fix reported clock rate in high bpc mode
* Drop hw_rate driver data
- Applied several tweaks to the following patches:
* Compute clk rate from PLL config
* Switch to driver specific HDMI config
* Add HDMI 2.1 FRL support
- Rebased series onto next-20250804
- Link to v1: https://lore.kernel.org/r/20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com
---
Cristian Ciocaltea (14):
phy: hdmi: Add HDMI 2.1 FRL configuration options
phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode
phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth
phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits
phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay()
phy: rockchip: samsung-hdptx: Fix coding style alignment
phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
phy: rockchip: samsung-hdptx: Enable lane output in common helper
phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists
phy: rockchip: samsung-hdptx: Compute clk rate from PLL config
phy: rockchip: samsung-hdptx: Drop hw_rate driver data
phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config
phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper
phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 697 ++++++++++++++++++----
include/linux/phy/phy-hdmi.h | 19 +-
2 files changed, 611 insertions(+), 105 deletions(-)
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base-commit: 3ac864c2d9bb8608ee236e89bf561811613abfce
change-id: 20250708-phy-hdptx-frl-fc3377db9f2e