Replace switch-case based speed-to-register conversion in DesignWare
driver with the newly introduced PCIE_SPEED2LNKCTL2_TLS() macro.
Signed-off-by: Hans Zhang <18255117159@163.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
drivers/pci/controller/dwc/pcie-designware.c | 18 +++---------------
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 89aad5a08928..d99f3bde847d 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -776,24 +776,12 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
- switch (pcie_link_speed[pci->max_link_speed]) {
- case PCIE_SPEED_2_5GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
- break;
- case PCIE_SPEED_5_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
- break;
- case PCIE_SPEED_8_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
- break;
- case PCIE_SPEED_16_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
- break;
- default:
+ link_speed = pcie_link_speed[pci->max_link_speed];
+ link_speed = PCIE_SPEED2LNKCTL2_TLS(link_speed);
+ if (link_speed == 0) {
/* Use hardware capability */
link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
- break;
}
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
--
2.25.1