In case of rx queue reset and 64bit capable hardware, set the upper
32bits of DMA ring buffer address.
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
drivers/net/ethernet/cadence/macb_main.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index ce95fad8cedd..41c0cbb5262e 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
macb_init_rx_ring(queue);
queue_writel(queue, RBQP, queue->rx_ring_dma);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+ if (bp->hw_dma_cap & HW_DMA_CAP_64B)
+ macb_writel(bp, RBQPH,
+ upper_32_bits(queue->rx_ring_dma));
+#endif
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
--
2.47.0On 15/08/2025 at 15:59, Stanimir Varbanov wrote: > In case of rx queue reset and 64bit capable hardware, set the upper > 32bits of DMA ring buffer address. Very nice finding! Thanks. > Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> A "Fixes" tag might be interesting here. > --- > drivers/net/ethernet/cadence/macb_main.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c > index ce95fad8cedd..41c0cbb5262e 100644 > --- a/drivers/net/ethernet/cadence/macb_main.c > +++ b/drivers/net/ethernet/cadence/macb_main.c > @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue, struct napi_struct *napi, > > macb_init_rx_ring(queue); > queue_writel(queue, RBQP, queue->rx_ring_dma); For the sake of consistency, I would add lower_32_bits() to this call, as I see it for each use of RBQP or TBQP. > +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT > + if (bp->hw_dma_cap & HW_DMA_CAP_64B) > + macb_writel(bp, RBQPH, > + upper_32_bits(queue->rx_ring_dma)); > +#endif > > macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); Best regards, Nicolas
Hi Nicolas,
On 8/19/25 11:29 AM, Nicolas Ferre wrote:
> On 15/08/2025 at 15:59, Stanimir Varbanov wrote:
>> In case of rx queue reset and 64bit capable hardware, set the upper
>> 32bits of DMA ring buffer address.
>
> Very nice finding! Thanks.
>
>> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
>
> A "Fixes" tag might be interesting here.
Looks like the commit is:
9ba723b081a2d ("net: macb: remove BUG_ON() and reset the queue to handle
RX errors")
>
>> ---
>> drivers/net/ethernet/cadence/macb_main.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/
>> ethernet/cadence/macb_main.c
>> index ce95fad8cedd..41c0cbb5262e 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue,
Also, the patch-set is adding a GEM variant but current patch is fixing
MACB. Could you please help us with testing on MACB and provide Tested-by?
>> struct napi_struct *napi,
>>
>> macb_init_rx_ring(queue);
>> queue_writel(queue, RBQP, queue->rx_ring_dma);
>
> For the sake of consistency, I would add lower_32_bits() to this call,
> as I see it for each use of RBQP or TBQP.
>
>> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
>> + if (bp->hw_dma_cap & HW_DMA_CAP_64B)
>> + macb_writel(bp, RBQPH,
>> + upper_32_bits(queue->rx_ring_dma));
>> +#endif
>>
>> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>
> Best regards,
> Nicolas
>
regards,
~Stan
Hi Nicolas, Thank you for the review! On 8/19/25 11:29 AM, Nicolas Ferre wrote: > On 15/08/2025 at 15:59, Stanimir Varbanov wrote: >> In case of rx queue reset and 64bit capable hardware, set the upper >> 32bits of DMA ring buffer address. > > Very nice finding! Thanks. Hmm, that reminds me that I have to update the patch body because the credits should go to Jonathan Bell and Phil Elwell if I decipher properly the description in raspberrypi downstream kernel :) > >> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> > > A "Fixes" tag might be interesting here. Sure, I'll do that. > >> --- >> drivers/net/ethernet/cadence/macb_main.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ >> ethernet/cadence/macb_main.c >> index ce95fad8cedd..41c0cbb5262e 100644 >> --- a/drivers/net/ethernet/cadence/macb_main.c >> +++ b/drivers/net/ethernet/cadence/macb_main.c >> @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue, >> struct napi_struct *napi, >> >> macb_init_rx_ring(queue); >> queue_writel(queue, RBQP, queue->rx_ring_dma); > > For the sake of consistency, I would add lower_32_bits() to this call, > as I see it for each use of RBQP or TBQP. Ack. > >> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT >> + if (bp->hw_dma_cap & HW_DMA_CAP_64B) >> + macb_writel(bp, RBQPH, >> + upper_32_bits(queue->rx_ring_dma)); >> +#endif >> >> macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); > > Best regards, > Nicolas > regards, ~Stan
On Fri, Aug 15, 2025 at 04:59:07PM +0300, Stanimir Varbanov wrote:
> In case of rx queue reset and 64bit capable hardware, set the upper
> 32bits of DMA ring buffer address.
>
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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