[v1] Adding device tree and binding for Nvidia mgx cx8 switchboard

[PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

Posted by Marc Olberding 1 month, 2 weeks ago

The mgx cx8 switchboard is used to network mgx GPUs

Signed-off-by: Marc Olberding <molberding@nvidia.com>
---
 .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    | 80 ++++++++++++++++++++++
 .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    | 80 ++++++++++++++++++++++
 2 files changed, 160 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..051c8cf0b7d12b1fa4c84db896ca480b21627e23
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+eeprom@56 {
+	compatible = "atmel,24c128";
+	reg = <0x56>;
+};
+
+gpio@26 {
+	compatible = "nxp,pca9555";
+	reg = <0x26>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	gpio-line-names = "WP_QSPI_CX0", "RST_SEQ_CX0_L",
+			  "BOOT_COMPLT_CX0", "FNP_CX0_L",
+			  "WP_FRU_CX0", "OVT_SHUTDOWN_CX0",
+			  "", "",
+			  "", "",
+			  "TMP_WARNING_CX0", "USB_HUB1_RST_L",
+			  "I2C_SWITCH1_RESET", "MCU1_GPIO",
+			  "MCU1_RST_N", "MCU1_RECOVERY_N";
+
+};
+
+i2c-mux@72 {
+	compatible = "nxp,pca9546";
+	reg = <0x72>;
+	i2c-mux-idle-disconnect;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+	};
+	i2c@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+	};
+	i2c@2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <2>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+	i2c@3 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <3>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+};
+
diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..cc8e71f374e100ba7f977138a21ea27a83ca36ed
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 Nvidia
+
+eeprom@56 {
+	compatible = "atmel,24c128";
+	reg = <0x56>;
+};
+
+gpio@26 {
+	compatible = "nxp,pca9555";
+	reg = <0x26>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	gpio-line-names = "WP_QSPI_CX1", "RST_SEQ_CX1_L",
+			  "BOOT_CMPLT_CX1", "FNP_CX1_L",
+			  "WP_FRU_CX1", "OVT_SHUTDOWN_CX1",
+			  "TMP_WARNING_CX1", "USB_HUB2_RST_L",
+			  "I2C_SWITCH2_RESET", "",
+			  "", "",
+			  "", "",
+			  "", "";
+};
+
+i2c-mux@72 {
+	compatible = "nxp,pca9546";
+	reg = <0x72>;
+	i2c-mux-idle-disconnect;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+	};
+	i2c@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+	};
+	i2c@2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <2>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+	i2c@3 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <3>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+};
+

-- 
2.34.1

Re: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

Posted by Krzysztof Kozlowski 1 month, 2 weeks ago

On 15/08/2025 21:45, Marc Olberding wrote:
> The mgx cx8 switchboard is used to network mgx GPUs
> 
> Signed-off-by: Marc Olberding <molberding@nvidia.com>
> ---
>  .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    | 80 ++++++++++++++++++++++
>  .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    | 80 ++++++++++++++++++++++
>  2 files changed, 160 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..051c8cf0b7d12b1fa4c84db896ca480b21627e23
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later

Odd license. Since when GPL-3.0 is okay?

> +
> +eeprom@56 {
> +	compatible = "atmel,24c128";
> +	reg = <0x56>;
> +};
> +

This is some completely misplaced DTSI style. Don't do this...

Best regards,
Krzysztof

Re: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

Posted by Marc Olberding 1 month, 2 weeks ago

On Sat, Aug 16, 2025 at 10:16:06AM +0200, Krzysztof Kozlowski wrote:
> 
> 
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> 
> Odd license. Since when GPL-3.0 is okay?
>
Ack, missed this. Will fix. 
> > +
> > +eeprom@56 {
> > +     compatible = "atmel,24c128";
> > +     reg = <0x56>;
> > +};
> > +
> 
> This is some completely misplaced DTSI style. Don't do this...

Thanks for the feedback. I'm not sure which piece of this is wrong.
Is the issue with having the contents of an i2c bus in a dtsi file?
If so, would you prefer that we abandon the dtsi all together and
add the contents in the dts file that's currently including it? This is
a seperate board from the one that the dts file describes, and others
may use it when integrating with the mgx-cx8 board, so the thought was to break it out
as a separate file. The only interface we have to describe between the two boards
is i2c, so this structure seemed appropriate. If not, I'll gladly get rid of it.

If its something other than the file structure, please let me know.

Best regards,
Marc Olberding

Re: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

Posted by Krzysztof Kozlowski 1 month, 2 weeks ago

On 19/08/2025 21:09, Marc Olberding wrote:
> On Sat, Aug 16, 2025 at 10:16:06AM +0200, Krzysztof Kozlowski wrote:
>>
>>
>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>
>> Odd license. Since when GPL-3.0 is okay?
>>
> Ack, missed this. Will fix. 
>>> +
>>> +eeprom@56 {
>>> +     compatible = "atmel,24c128";
>>> +     reg = <0x56>;
>>> +};
>>> +
>>
>> This is some completely misplaced DTSI style. Don't do this...
> 
> Thanks for the feedback. I'm not sure which piece of this is wrong.
> Is the issue with having the contents of an i2c bus in a dtsi file?
> If so, would you prefer that we abandon the dtsi all together and

I think this should be just included in each bus needing it. It's really
odd to see a DTSI with top-level I2C devices.

Best regards,
Krzysztof