The bit range 17:0 does not match the datasheet for A311D / S905D3.
Change the bit range to 19:0 for FIX and HIFI PLLs to match datasheet.

There's no frac for sys pll so add that as well.

Signed-off-by: Da Xue <da@libre.computer>
---
 drivers/clk/meson/g12a.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 66f0e817e416..f78cca619ca5 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -157,7 +157,7 @@ static struct clk_regmap g12a_fixed_pll_dco = {
 		.frac = {
 			.reg_off = HHI_FIX_PLL_CNTL1,
 			.shift   = 0,
-			.width   = 17,
+			.width   = 19,
 		},
 		.l = {
 			.reg_off = HHI_FIX_PLL_CNTL0,
@@ -223,6 +223,11 @@ static struct clk_regmap g12a_sys_pll_dco = {
 			.shift   = 10,
 			.width   = 5,
 		},
+		.frac = {
+			.reg_off = HHI_SYS_PLL_CNTL1,
+			.shift   = 0,
+			.width   = 19,
+		},
 		.l = {
 			.reg_off = HHI_SYS_PLL_CNTL0,
 			.shift   = 31,
@@ -1901,7 +1906,7 @@ static struct clk_regmap g12a_hifi_pll_dco = {
 		.frac = {
 			.reg_off = HHI_HIFI_PLL_CNTL1,
 			.shift   = 0,
-			.width   = 17,
+			.width   = 19,
 		},
 		.l = {
 			.reg_off = HHI_HIFI_PLL_CNTL0,
-- 
2.47.2

On Thu, Aug 14, 2025 at 10:09 PM Da Xue <da@libre.computer> wrote:
>
> The bit range 17:0 does not match the datasheet for A311D / S905D3.
> Change the bit range to 19:0 for FIX and HIFI PLLs to match datasheet.
I have:
-  S905X3_Public_Datasheet_Hardkernel.pdf
-  S922X_Datasheet_Wesion.pdf
-  A311D_Datasheet_01_Wesion.pdf
These state (for all three PLLs) that .frac is [18:0] (that's shift =
0 and width = 19).
I get where you're coming from with 19:0 - in the context of this
patch this can be misleading as it would mean that the fractional
divider is 20 bits wide.

> There's no frac for sys pll so add that as well.
I first read this as sys pll does not have a fractional divider.
What do you think about: "The frac field for sys pll is missing so add
that as well"

I guess at this point this should include:
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Da Xue <da@libre.computer>

[...]
Have you compared /sys/kernel/debug/meson-clk-msr/measure_summary and
/sys/kernel/debug/clk/clk_summary before/after this patch?
I'll test this during the weekend and then give my Tested/Reviewed by


Best regards,
Martin

On Thu, Aug 21, 2025 at 4:43 PM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> On Thu, Aug 14, 2025 at 10:09 PM Da Xue <da@libre.computer> wrote:
> >
> > The bit range 17:0 does not match the datasheet for A311D / S905D3.
> > Change the bit range to 19:0 for FIX and HIFI PLLs to match datasheet.
> I have:
> -  S905X3_Public_Datasheet_Hardkernel.pdf
> -  S922X_Datasheet_Wesion.pdf
> -  A311D_Datasheet_01_Wesion.pdf
> These state (for all three PLLs) that .frac is [18:0] (that's shift =
> 0 and width = 19).
> I get where you're coming from with 19:0 - in the context of this
> patch this can be misleading as it would mean that the fractional
> divider is 20 bits wide.

Yes, I was in a rush and missed this. The description is bad and I'll
spin a v2 with the Fixes as well as report the clock differences.

>
> > There's no frac for sys pll so add that as well.
> I first read this as sys pll does not have a fractional divider.
> What do you think about: "The frac field for sys pll is missing so add
> that as well"

Will correct in V2.

>
> I guess at this point this should include:
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> > Signed-off-by: Da Xue <da@libre.computer>

Ack
>
> [...]
> Have you compared /sys/kernel/debug/meson-clk-msr/measure_summary and
> /sys/kernel/debug/clk/clk_summary before/after this patch?
> I'll test this during the weekend and then give my Tested/Reviewed by

Will provide in V2.

>
>
> Best regards,
> Martin