On 01/09/2025 11:05 am, Leo Yan wrote:
> On Thu, Aug 14, 2025 at 10:25:27AM +0100, James Clark wrote:
>> We check the version of SPE twice, and we'll add one more check in the
>> next commit so factor out a macro to do this. Change the #3 magic number
>> to the actual SPE version define (V1p2) to make it more readable.
>>
>> No functional changes intended.
>>
>> Tested-by: Leo Yan <leo.yan@arm.com>
>> Signed-off-by: James Clark <james.clark@linaro.org>
>> ---
>> arch/arm64/include/asm/el2_setup.h | 17 +++++++++++------
>> 1 file changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
>> index 46033027510c..3a4ca7f9acfb 100644
>> --- a/arch/arm64/include/asm/el2_setup.h
>> +++ b/arch/arm64/include/asm/el2_setup.h
>> @@ -103,8 +103,7 @@
>> csel x2, xzr, x0, eq // all PMU counters from EL1
>>
>> /* Statistical profiling */
>> - ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
>> - cbz x0, .Lskip_spe_\@ // Skip if SPE not present
>> + __spe_vers_imp .Lskip_spe_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x0 // Skip if SPE not present
>>
>> mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
>> and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT)
>> @@ -255,6 +254,14 @@
>> .Lskip_brbe_\@:
>> .endm
>>
>> +/* Branch to skip_label if SPE version is less than given version */
>> +.macro __spe_vers_imp skip_label, version, tmp
>> + mrs \tmp, id_aa64dfr0_el1
>> + ubfx \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
>> + cmp \tmp, \version
>> + b.lt \skip_label
>> +.endm
>> +
>
> Just wondering if we need to move the macro to the beginning of the
> file, so that we can define it first and call it afterwards.
>
> Otherwise, LGTM:
>
> Reviewed-by: Leo Yan <leo.yan@arm.com>
>
It's not required, but all the other macros are defined before use and
it looks a bit weird to not do it, so I can move it.
>> /* Disable any fine grained traps */
>> .macro __init_el2_fgt
>> mrs x1, id_aa64mmfr0_el1
>> @@ -263,10 +270,8 @@
>>
>> mov x0, xzr
>> mov x2, xzr
>> - mrs x1, id_aa64dfr0_el1
>> - ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
>> - cmp x1, #3
>> - b.lt .Lskip_spe_fgt_\@
>> + /* If SPEv1p2 is implemented, */
>> + __spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1
>> /* Disable PMSNEVFR_EL1 read and write traps */
>> orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK
>> orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK
>>
>> --
>> 2.34.1
>>