Add the Device Tree binding for the PCIe root complex found on the
SpacemiT K1 SoC. This device is derived from the Synopsys Designware
PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
typically used to support a USB 3 port.
Signed-off-by: Alex Elder <elder@riscstar.com>
---
.../bindings/pci/spacemit,k1-pcie-rc.yaml | 141 ++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
new file mode 100644
index 0000000000000..6bcca2f91a6fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-rc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCI Express Root Complex
+
+maintainers:
+ - Alex Elder <elder@riscstar.com>
+
+description:
+ The SpacemiT K1 SoC PCIe root complex controller is based on the
+ Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: spacemit,k1-pcie-rc.yaml
+
+ reg:
+ items:
+ - description: DesignWare PCIe registers
+ - description: ATU address space
+ - description: PCIe configuration space
+ - description: Link control registers
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: atu
+ - const: config
+ - const: link
+
+ clocks:
+ items:
+ - description: DWC PCIe Data Bus Interface (DBI) clock
+ - description: DWC PCIe application AXI-bus Master interface clock
+ - description: DWC PCIe application AXI-bus Slave interface clock.
+
+ clock-names:
+ items:
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ resets:
+ items:
+ - description: DWC PCIe Data Bus Interface (DBI) reset
+ - description: DWC PCIe application AXI-bus Master interface reset
+ - description: DWC PCIe application AXI-bus Slave interface reset.
+ - description: Global reset; must be deasserted for PHY to function
+
+ reset-names:
+ items:
+ - const: dbi
+ - const: mstr
+ - const: slv
+ - const: global
+
+ interrupts-extended:
+ maxItems: 1
+
+ spacemit,syscon-pmu:
+ description:
+ PHandle that refers to the APMU system controller, whose
+ regmap is used in managing resets and link state.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ device_type:
+ const: pci
+
+ max-link-speed:
+ const: 2
+
+ num-viewport:
+ const: 8
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - spacemit,syscon-pmu
+ - "#address-cells"
+ - "#size-cells"
+ - device_type
+ - max-link-speed
+ - bus-range
+ - num-viewport
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ pcie0: pcie@ca000000 {
+ compatible = "spacemit,k1-pcie-rc";
+ reg = <0x0 0xca000000 0x0 0x00001000>,
+ <0x0 0xca300000 0x0 0x0001ff24>,
+ <0x0 0x8f000000 0x0 0x00002000>,
+ <0x0 0xc0b20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+
+ ranges = <0x01000000 0x8f002000 0x0 0x8f002000 0x0 0x100000>,
+ <0x02000000 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
+
+ clocks = <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+
+ resets = <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>,
+ <&syscon_apmu RESET_PCIE0_GLOBAL>;
+ reset-names = "dbi",
+ "mstr",
+ "slv",
+ "global";
+
+ interrupts-extended = <&plic 141>;
+
+ spacemit,syscon-pmu = <&syscon_apmu 0x03cc>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-viewport = <8>;
+
+ status = "disabled";
+ };
--
2.48.1On Wed, Aug 13, 2025 at 01:46:57PM GMT, Alex Elder wrote:
Subject should have 'pci' prefix, not 'phy'.
> Add the Device Tree binding for the PCIe root complex found on the
> SpacemiT K1 SoC. This device is derived from the Synopsys Designware
> PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
> link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
> typically used to support a USB 3 port.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> .../bindings/pci/spacemit,k1-pcie-rc.yaml | 141 ++++++++++++++++++
> 1 file changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
> new file mode 100644
> index 0000000000000..6bcca2f91a6fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-rc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 PCI Express Root Complex
> +
> +maintainers:
> + - Alex Elder <elder@riscstar.com>
> +
> +description:
> + The SpacemiT K1 SoC PCIe root complex controller is based on the
> + Synopsys DesignWare PCIe IP.
> +
> +properties:
> + compatible:
> + const: spacemit,k1-pcie-rc.yaml
> +
> + reg:
> + items:
> + - description: DesignWare PCIe registers
> + - description: ATU address space
> + - description: PCIe configuration space
> + - description: Link control registers
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: atu
> + - const: config
> + - const: link
> +
> + clocks:
> + items:
> + - description: DWC PCIe Data Bus Interface (DBI) clock
> + - description: DWC PCIe application AXI-bus Master interface clock
> + - description: DWC PCIe application AXI-bus Slave interface clock.
> +
> + clock-names:
> + items:
> + - const: dbi
> + - const: mstr
> + - const: slv
> +
> + resets:
> + items:
> + - description: DWC PCIe Data Bus Interface (DBI) reset
> + - description: DWC PCIe application AXI-bus Master interface reset
> + - description: DWC PCIe application AXI-bus Slave interface reset.
> + - description: Global reset; must be deasserted for PHY to function
> +
> + reset-names:
> + items:
> + - const: dbi
> + - const: mstr
> + - const: slv
> + - const: global
> +
> + interrupts-extended:
> + maxItems: 1
What is the purpose of this property? Is it for MSI or INTx?
> +
> + spacemit,syscon-pmu:
> + description:
> + PHandle that refers to the APMU system controller, whose
> + regmap is used in managing resets and link state.
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> + device_type:
> + const: pci
> +
> + max-link-speed:
> + const: 2
Why do you need to limit it to 5 GT/s always?
> +
> + num-viewport:
> + const: 8
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - spacemit,syscon-pmu
> + - "#address-cells"
> + - "#size-cells"
> + - device_type
> + - max-link-speed
Same comment as above.
> + - bus-range
> + - num-viewport
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/spacemit,k1-syscon.h>
> + pcie0: pcie@ca000000 {
> + compatible = "spacemit,k1-pcie-rc";
> + reg = <0x0 0xca000000 0x0 0x00001000>,
> + <0x0 0xca300000 0x0 0x0001ff24>,
> + <0x0 0x8f000000 0x0 0x00002000>,
> + <0x0 0xc0b20000 0x0 0x00001000>;
> + reg-names = "dbi",
> + "atu",
> + "config",
> + "link";
> +
> + ranges = <0x01000000 0x8f002000 0x0 0x8f002000 0x0 0x100000>,
I/O port CPU address starts from 0.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 9/15/25 3:14 AM, Manivannan Sadhasivam wrote:
> On Wed, Aug 13, 2025 at 01:46:57PM GMT, Alex Elder wrote:
>
> Subject should have 'pci' prefix, not 'phy'.
OK I'll update that in the next version.
>> Add the Device Tree binding for the PCIe root complex found on the
>> SpacemiT K1 SoC. This device is derived from the Synopsys Designware
>> PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
>> link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
>> typically used to support a USB 3 port.
>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> .../bindings/pci/spacemit,k1-pcie-rc.yaml | 141 ++++++++++++++++++
>> 1 file changed, 141 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
>> new file mode 100644
>> index 0000000000000..6bcca2f91a6fd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
>> @@ -0,0 +1,141 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-rc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: SpacemiT K1 PCI Express Root Complex
>> +
>> +maintainers:
>> + - Alex Elder <elder@riscstar.com>
>> +
>> +description:
>> + The SpacemiT K1 SoC PCIe root complex controller is based on the
>> + Synopsys DesignWare PCIe IP.
>> +
>> +properties:
>> + compatible:
>> + const: spacemit,k1-pcie-rc.yaml
>> +
>> + reg:
>> + items:
>> + - description: DesignWare PCIe registers
>> + - description: ATU address space
>> + - description: PCIe configuration space
>> + - description: Link control registers
>> +
>> + reg-names:
>> + items:
>> + - const: dbi
>> + - const: atu
>> + - const: config
>> + - const: link
>> +
>> + clocks:
>> + items:
>> + - description: DWC PCIe Data Bus Interface (DBI) clock
>> + - description: DWC PCIe application AXI-bus Master interface clock
>> + - description: DWC PCIe application AXI-bus Slave interface clock.
>> +
>> + clock-names:
>> + items:
>> + - const: dbi
>> + - const: mstr
>> + - const: slv
>> +
>> + resets:
>> + items:
>> + - description: DWC PCIe Data Bus Interface (DBI) reset
>> + - description: DWC PCIe application AXI-bus Master interface reset
>> + - description: DWC PCIe application AXI-bus Slave interface reset.
>> + - description: Global reset; must be deasserted for PHY to function
>> +
>> + reset-names:
>> + items:
>> + - const: dbi
>> + - const: mstr
>> + - const: slv
>> + - const: global
>> +
>> + interrupts-extended:
>> + maxItems: 1
>
> What is the purpose of this property? Is it for MSI or INTx?
It is for MSIs, which are translated into this interrupt.
I'll add a short description indicating this.
Is there a better way to represent this?
>> +
>> + spacemit,syscon-pmu:
>> + description:
>> + PHandle that refers to the APMU system controller, whose
>> + regmap is used in managing resets and link state.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> + device_type:
>> + const: pci
>> +
>> + max-link-speed:
>> + const: 2
>
> Why do you need to limit it to 5 GT/s always?
It's what the hardware overview says is the speed
of the ports.
PCIE PortA Gen2x1
PCIE PortB Gen2x2
PCIE PortC Gen2x2
But I think what you're asking might be "why do you
need to specify in DT that the link speed is limited".
And in that case, I realize now that it is not needed.
I will specify dw_pcie->max_link_speed to 2 before
calling dw_pcie_host_init().
If that's not what you meant, please let me know.
>> + num-viewport:
>> + const: 8
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - spacemit,syscon-pmu
>> + - "#address-cells"
>> + - "#size-cells"
>> + - device_type
>> + - max-link-speed
>
> Same comment as above.
>
>> + - bus-range
>> + - num-viewport
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/spacemit,k1-syscon.h>
>> + pcie0: pcie@ca000000 {
>> + compatible = "spacemit,k1-pcie-rc";
>> + reg = <0x0 0xca000000 0x0 0x00001000>,
>> + <0x0 0xca300000 0x0 0x0001ff24>,
>> + <0x0 0x8f000000 0x0 0x00002000>,
>> + <0x0 0xc0b20000 0x0 0x00001000>;
>> + reg-names = "dbi",
>> + "atu",
>> + "config",
>> + "link";
>> +
>> + ranges = <0x01000000 0x8f002000 0x0 0x8f002000 0x0 0x100000>,
>
> I/O port CPU address starts from 0.
First, I'm not sure what this comment means.
But second, this ranges value (which I'm sure I just copied from
the working DTS file) somehow got munged.
I know there were other errors in this YAML file that I have
to fix, and I'll fix this too.
Thank you Mani.
-Alex
>
> - Mani
>
On Wed, 13 Aug 2025 13:46:57 -0500, Alex Elder wrote: > Add the Device Tree binding for the PCIe root complex found on the > SpacemiT K1 SoC. This device is derived from the Synopsys Designware > PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2 > link speeds (5 GT/sec). One of the ports uses a combo PHY, which is > typically used to support a USB 3 port. > > Signed-off-by: Alex Elder <elder@riscstar.com> > --- > .../bindings/pci/spacemit,k1-pcie-rc.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.example.dtb: /example-0/pcie@ca000000: failed to match any schema with compatible: ['spacemit,k1-pcie-rc'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250813184701.2444372-4-elder@riscstar.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 8/13/25 3:49 PM, Rob Herring (Arm) wrote: > > On Wed, 13 Aug 2025 13:46:57 -0500, Alex Elder wrote: >> Add the Device Tree binding for the PCIe root complex found on the >> SpacemiT K1 SoC. This device is derived from the Synopsys Designware >> PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2 >> link speeds (5 GT/sec). One of the ports uses a combo PHY, which is >> typically used to support a USB 3 port. >> >> Signed-off-by: Alex Elder <elder@riscstar.com> >> --- >> .../bindings/pci/spacemit,k1-pcie-rc.yaml | 141 ++++++++++++++++++ >> 1 file changed, 141 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml >> > > My bot found errors running 'make dt_binding_check' on your patch: Mine didn't for some reason, so I must be doing something wrong. Simple inspection shows my compatible string contains ".yaml"! I'll fix in a new version. Sorry I missed this. -Alex > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.example.dtb: /example-0/pcie@ca000000: failed to match any schema with compatible: ['spacemit,k1-pcie-rc'] > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250813184701.2444372-4-elder@riscstar.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. >
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