[PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0

Icenowy Zheng posted 2 patches 1 month, 3 weeks ago
There is a newer version of this series
drivers/clk/thead/clk-th1520-ap.c | 385 +++++++++++++++---------------
1 file changed, 188 insertions(+), 197 deletions(-)
[PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0
Posted by Icenowy Zheng 1 month, 3 weeks ago
Current ccu_gate implementation does not easily allow gates to be clock
parents because of the waste of struct clk_hw in struct ccu_gate;
however it's found that the padctrl0 apb clock gate seems to be
downstream of perisys-apb4-hclk, gating the latter w/o gating the former
makes the padctrl0 registers inaccessible too.

Fix this by refactor ccu_gate code, mimicing what Yao Zi did on
ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus
gate.

This patchset depends on the display clock patchset at [1], although a
rebasing to get rid of this dependency is possible.

[1] https://lore.kernel.org/linux-riscv/20250813072702.2176993-1-uwu@icenowy.me/

Icenowy Zheng (2):
  clk: thead: th1520-ap: describe gate clocks with clk_gate
  clk: thead: th1520-ap: fix parent of padctrl0 clock

 drivers/clk/thead/clk-th1520-ap.c | 385 +++++++++++++++---------------
 1 file changed, 188 insertions(+), 197 deletions(-)

-- 
2.50.1
Re: [PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0
Posted by Icenowy Zheng 1 month, 3 weeks ago
在 2025-08-14星期四的 01:11 +0800,Icenowy Zheng写道:
> Current ccu_gate implementation does not easily allow gates to be
> clock
> parents because of the waste of struct clk_hw in struct ccu_gate;
> however it's found that the padctrl0 apb clock gate seems to be
> downstream of perisys-apb4-hclk, gating the latter w/o gating the
> former
> makes the padctrl0 registers inaccessible too.
> 
> Fix this by refactor ccu_gate code, mimicing what Yao Zi did on
> ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus
> gate.

Forgot to mention a easy test of this patchset:

Just install `gpioset` from `libgpiod` on a Lichee Pi 4A, plug a fan to
its fan port, and run `gpioset 3 3=1`. The expected behavior is the fan
starts to spin (because GPIO3_3 is the pin controlling the fan),
however without this patchset Linux will fail to switch that pin.

> 
> This patchset depends on the display clock patchset at [1], although
> a
> rebasing to get rid of this dependency is possible.
> 
> [1]
> https://lore.kernel.org/linux-riscv/20250813072702.2176993-1-uwu@icenowy.me/
> 
> Icenowy Zheng (2):
>   clk: thead: th1520-ap: describe gate clocks with clk_gate
>   clk: thead: th1520-ap: fix parent of padctrl0 clock
> 
>  drivers/clk/thead/clk-th1520-ap.c | 385 +++++++++++++++-------------
> --
>  1 file changed, 188 insertions(+), 197 deletions(-)
> 
Re: [PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0
Posted by Drew Fustini 1 month, 2 weeks ago
On Thu, Aug 14, 2025 at 01:16:16AM +0800, Icenowy Zheng wrote:
> 在 2025-08-14星期四的 01:11 +0800,Icenowy Zheng写道:
> > Current ccu_gate implementation does not easily allow gates to be
> > clock
> > parents because of the waste of struct clk_hw in struct ccu_gate;
> > however it's found that the padctrl0 apb clock gate seems to be
> > downstream of perisys-apb4-hclk, gating the latter w/o gating the
> > former
> > makes the padctrl0 registers inaccessible too.
> > 
> > Fix this by refactor ccu_gate code, mimicing what Yao Zi did on
> > ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus
> > gate.
> 
> Forgot to mention a easy test of this patchset:
> 
> Just install `gpioset` from `libgpiod` on a Lichee Pi 4A, plug a fan to
> its fan port, and run `gpioset 3 3=1`. The expected behavior is the fan
> starts to spin (because GPIO3_3 is the pin controlling the fan),
> however without this patchset Linux will fail to switch that pin.

Thanks. That worked great and the fan is spinning :)

Drew
Re: [PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0
Posted by Guo Ren 1 month, 3 weeks ago
Thanks for the fixup, don't forget the "Fixes" tag and Cc stable@kernel.org.

Others LGTM!

Reviewed-by: Guo Ren <guoren@kernel.org>

On Thu, Aug 14, 2025 at 1:16 AM Icenowy Zheng <uwu@icenowy.me> wrote:
>
> 在 2025-08-14星期四的 01:11 +0800,Icenowy Zheng写道:
> > Current ccu_gate implementation does not easily allow gates to be
> > clock
> > parents because of the waste of struct clk_hw in struct ccu_gate;
> > however it's found that the padctrl0 apb clock gate seems to be
> > downstream of perisys-apb4-hclk, gating the latter w/o gating the
> > former
> > makes the padctrl0 registers inaccessible too.
> >
> > Fix this by refactor ccu_gate code, mimicing what Yao Zi did on
> > ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus
> > gate.
>
> Forgot to mention a easy test of this patchset:
>
> Just install `gpioset` from `libgpiod` on a Lichee Pi 4A, plug a fan to
> its fan port, and run `gpioset 3 3=1`. The expected behavior is the fan
> starts to spin (because GPIO3_3 is the pin controlling the fan),
> however without this patchset Linux will fail to switch that pin.
>
> >
> > This patchset depends on the display clock patchset at [1], although
> > a
> > rebasing to get rid of this dependency is possible.
> >
> > [1]
> > https://lore.kernel.org/linux-riscv/20250813072702.2176993-1-uwu@icenowy.me/
> >
> > Icenowy Zheng (2):
> >   clk: thead: th1520-ap: describe gate clocks with clk_gate
> >   clk: thead: th1520-ap: fix parent of padctrl0 clock
> >
> >  drivers/clk/thead/clk-th1520-ap.c | 385 +++++++++++++++-------------
> > --
> >  1 file changed, 188 insertions(+), 197 deletions(-)
> >
>


-- 
Best Regards
 Guo Ren