The 2nd control word of T-Head TH1520 PLLs contains a bit to put the VCO
into reset state, which means disabling the PLL.
Some PLLs are put to disabled state by the bootloader, and the clock
driver should be able to enable them.
Add support for enabling/disabling PLLs. PLLs other than DPU ones are
set CLK_IS_CRITICAL to prevent killing the system -- they're meant to
drive CPU or system buses (even the GMAC/Video ones are driving arbitrary
buses).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
No changes in v2.
drivers/clk/thead/clk-th1520-ap.c | 38 +++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
index dd6359441f7e8..0b5458af8c550 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -18,6 +18,7 @@
#define TH1520_PLL_FBDIV GENMASK(19, 8)
#define TH1520_PLL_REFDIV GENMASK(5, 0)
#define TH1520_PLL_BYPASS BIT(30)
+#define TH1520_PLL_VCO_RST BIT(29)
#define TH1520_PLL_DSMPD BIT(24)
#define TH1520_PLL_FRAC GENMASK(23, 0)
#define TH1520_PLL_FRAC_BITS 24
@@ -242,6 +243,30 @@ static const struct clk_ops ccu_div_ops = {
.determine_rate = clk_hw_determine_rate_no_reparent,
};
+static void ccu_pll_disable(struct clk_hw *hw)
+{
+ struct ccu_pll *pll = hw_to_ccu_pll(hw);
+
+ regmap_set_bits(pll->common.map, pll->common.cfg1,
+ TH1520_PLL_VCO_RST);
+}
+
+static int ccu_pll_enable(struct clk_hw *hw)
+{
+ struct ccu_pll *pll = hw_to_ccu_pll(hw);
+
+ return regmap_clear_bits(pll->common.map, pll->common.cfg1,
+ TH1520_PLL_VCO_RST);
+}
+
+static int ccu_pll_is_enabled(struct clk_hw *hw)
+{
+ struct ccu_pll *pll = hw_to_ccu_pll(hw);
+
+ return !regmap_test_bits(pll->common.map, pll->common.cfg1,
+ TH1520_PLL_VCO_RST);
+}
+
static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -299,6 +324,9 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
}
static const struct clk_ops clk_pll_ops = {
+ .disable = ccu_pll_disable,
+ .enable = ccu_pll_enable,
+ .is_enabled = ccu_pll_is_enabled,
.recalc_rate = ccu_pll_recalc_rate,
};
@@ -314,7 +342,7 @@ static struct ccu_pll cpu_pll0_clk = {
.hw.init = CLK_HW_INIT_PARENTS_DATA("cpu-pll0",
osc_24m_clk,
&clk_pll_ops,
- 0),
+ CLK_IS_CRITICAL),
},
};
@@ -326,7 +354,7 @@ static struct ccu_pll cpu_pll1_clk = {
.hw.init = CLK_HW_INIT_PARENTS_DATA("cpu-pll1",
osc_24m_clk,
&clk_pll_ops,
- 0),
+ CLK_IS_CRITICAL),
},
};
@@ -338,7 +366,7 @@ static struct ccu_pll gmac_pll_clk = {
.hw.init = CLK_HW_INIT_PARENTS_DATA("gmac-pll",
osc_24m_clk,
&clk_pll_ops,
- 0),
+ CLK_IS_CRITICAL),
},
};
@@ -358,7 +386,7 @@ static struct ccu_pll video_pll_clk = {
.hw.init = CLK_HW_INIT_PARENTS_DATA("video-pll",
osc_24m_clk,
&clk_pll_ops,
- 0),
+ CLK_IS_CRITICAL),
},
};
@@ -410,7 +438,7 @@ static struct ccu_pll tee_pll_clk = {
.hw.init = CLK_HW_INIT_PARENTS_DATA("tee-pll",
osc_24m_clk,
&clk_pll_ops,
- 0),
+ CLK_IS_CRITICAL),
},
};
--
2.50.1
On Wed, Aug 13, 2025 at 03:27:00PM +0800, Icenowy Zheng wrote: > The 2nd control word of T-Head TH1520 PLLs contains a bit to put the VCO > into reset state, which means disabling the PLL. > > Some PLLs are put to disabled state by the bootloader, and the clock > driver should be able to enable them. > > Add support for enabling/disabling PLLs. PLLs other than DPU ones are > set CLK_IS_CRITICAL to prevent killing the system -- they're meant to > drive CPU or system buses (even the GMAC/Video ones are driving arbitrary > buses). Do you think there is a way in the future to allow disabling PLLs for run-time power management? I think it is more important right now to get hardware peripherals working upstream like you are doing, but I was curious if there is the potential to do something more granular in the future. > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > No changes in v2. > > drivers/clk/thead/clk-th1520-ap.c | 38 +++++++++++++++++++++++++++---- > 1 file changed, 33 insertions(+), 5 deletions(-) Reviewed-by: Drew Fustini <fustini@kernel.org>
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