Add the compatible string "qcom,qcs8300-camss" to support the
Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform.
The QCS8300 platform provides:
- 2 x VFE (version 690), each with 3 RDI
- 5 x VFE Lite (version 690), each with 6 RDI
- 2 x CSID (version 690)
- 5 x CSID Lite (version 690)
- 3 x CSIPHY (version 690)
- 3 x TPG
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/media/qcom,qcs8300-camss.yaml | 336 ++++++++++++++++++
1 file changed, 336 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
new file mode 100644
index 000000000000..80a4540a22dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
@@ -0,0 +1,336 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS8300 CAMSS ISP
+
+maintainers:
+ - Vikram Sharma <quic_vikramsa@quicinc.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,qcs8300-camss
+
+ reg:
+ maxItems: 21
+
+ reg-names:
+ items:
+ - const: csid_wrapper
+ - const: csid0
+ - const: csid1
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_lite2
+ - const: csid_lite3
+ - const: csid_lite4
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe_lite2
+ - const: vfe_lite3
+ - const: vfe_lite4
+
+ clocks:
+ maxItems: 26
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: cpas_fast_ahb_clk
+ - const: cpas_vfe_lite
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: csid
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: icp_ahb
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 20
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_lite2
+ - const: csid_lite3
+ - const: csid_lite4
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe_lite2
+ - const: vfe_lite3
+ - const: vfe_lite4
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-2]+$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 0-2.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+ #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac78000 {
+ compatible = "qcom,qcs8300-camss";
+
+ reg = <0x0 0xac78000 0x0 0x1000>,
+ <0x0 0xac7a000 0x0 0x0f00>,
+ <0x0 0xac7c000 0x0 0x0f00>,
+ <0x0 0xac84000 0x0 0x0f00>,
+ <0x0 0xac88000 0x0 0x0f00>,
+ <0x0 0xac8c000 0x0 0x0f00>,
+ <0x0 0xac90000 0x0 0x0f00>,
+ <0x0 0xac94000 0x0 0x0f00>,
+ <0x0 0xac9c000 0x0 0x2000>,
+ <0x0 0xac9e000 0x0 0x2000>,
+ <0x0 0xaca0000 0x0 0x2000>,
+ <0x0 0xacac000 0x0 0x0400>,
+ <0x0 0xacad000 0x0 0x0400>,
+ <0x0 0xacae000 0x0 0x0400>,
+ <0x0 0xac4d000 0x0 0xd000>,
+ <0x0 0xac60000 0x0 0xd000>,
+ <0x0 0xac85000 0x0 0x0d00>,
+ <0x0 0xac89000 0x0 0x0d00>,
+ <0x0 0xac8d000 0x0 0x0d00>,
+ <0x0 0xac91000 0x0 0x0d00>,
+ <0x0 0xac95000 0x0 0x0d00>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb_clk",
+ "cpas_vfe_lite",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0";
+
+ iommus = <&apps_smmu 0x2400 0x20>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "top";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.25.1On 13/08/2025 07:37, Vikram Sharma wrote: > Add the compatible string "qcom,qcs8300-camss" to support the > Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. > > The QCS8300 platform provides: > - 2 x VFE (version 690), each with 3 RDI > - 5 x VFE Lite (version 690), each with 6 RDI > - 2 x CSID (version 690) > - 5 x CSID Lite (version 690) > - 3 x CSIPHY (version 690) > - 3 x TPG > > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/media/qcom,qcs8300-camss.yaml | 336 ++++++++++++++++++ > 1 file changed, 336 insertions(+) So it turns out this code is wrong and you already sent fixes for it. Bryan, please don't apply it. Best regards, Krzysztof
On 9/10/2025 12:35 PM, Krzysztof Kozlowski wrote: > On 13/08/2025 07:37, Vikram Sharma wrote: >> Add the compatible string "qcom,qcs8300-camss" to support the >> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >> >> The QCS8300 platform provides: >> - 2 x VFE (version 690), each with 3 RDI >> - 5 x VFE Lite (version 690), each with 6 RDI >> - 2 x CSID (version 690) >> - 5 x CSID Lite (version 690) >> - 3 x CSIPHY (version 690) >> - 3 x TPG >> >> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- >> .../bindings/media/qcom,qcs8300-camss.yaml | 336 ++++++++++++++++++ >> 1 file changed, 336 insertions(+) > So it turns out this code is wrong and you already sent fixes for it. Hi Krzysztof, Thanks for your comments. These bindings are tested with TPG (Test Pattern Generator), As camera sensor testing was not possible at that point. This is because Monaco-evk kit was not ready which can be used to enable sensor. These Bindings are complete in its own, If someone want to use TPG. My latest update in these bindings are for camera sensor enablement which needs supplies too. Please let me know if this justification works to accept these bindings it its current form and add supplies as a separate patch. Best regards, Vikram > > Bryan, please don't apply it. > > Best regards, > Krzysztof
On 10/09/2025 09:26, Vikram Sharma wrote: > > On 9/10/2025 12:35 PM, Krzysztof Kozlowski wrote: >> On 13/08/2025 07:37, Vikram Sharma wrote: >>> Add the compatible string "qcom,qcs8300-camss" to support the >>> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >>> >>> The QCS8300 platform provides: >>> - 2 x VFE (version 690), each with 3 RDI >>> - 5 x VFE Lite (version 690), each with 6 RDI >>> - 2 x CSID (version 690) >>> - 5 x CSID Lite (version 690) >>> - 3 x CSIPHY (version 690) >>> - 3 x TPG >>> >>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> --- >>> .../bindings/media/qcom,qcs8300-camss.yaml | 336 ++++++++++++++++++ >>> 1 file changed, 336 insertions(+) >> So it turns out this code is wrong and you already sent fixes for it. > > Hi Krzysztof, > Thanks for your comments. These bindings are tested with TPG (Test Pattern Generator), As camera sensor testing was not possible at that point. You cannot test bindings with TPG. It's impossible. > This is because Monaco-evk kit was not ready which can be used to enable sensor. > > These Bindings are complete in its own, If someone want to use TPG. No. You do not understand - they are not complete if you add new properties to them! How bindings could be complete if you add now supplies!?!? > > My latest update in these bindings are for camera sensor enablement which needs supplies too. > > Please let me know if this justification works to accept these bindings it its current form and add supplies as a separate patch. NAK. Read writing bindings doc. Or internal docs. Best regards, Krzysztof
On 10/09/2025 08:42, Krzysztof Kozlowski wrote: > On 10/09/2025 09:26, Vikram Sharma wrote: >> >> On 9/10/2025 12:35 PM, Krzysztof Kozlowski wrote: >>> On 13/08/2025 07:37, Vikram Sharma wrote: >>>> Add the compatible string "qcom,qcs8300-camss" to support the >>>> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >>>> >>>> The QCS8300 platform provides: >>>> - 2 x VFE (version 690), each with 3 RDI >>>> - 5 x VFE Lite (version 690), each with 6 RDI >>>> - 2 x CSID (version 690) >>>> - 5 x CSID Lite (version 690) >>>> - 3 x CSIPHY (version 690) >>>> - 3 x TPG >>>> >>>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>>> --- >>>> .../bindings/media/qcom,qcs8300-camss.yaml | 336 ++++++++++++++++++ >>>> 1 file changed, 336 insertions(+) >>> So it turns out this code is wrong and you already sent fixes for it. >> >> Hi Krzysztof, >> Thanks for your comments. These bindings are tested with TPG (Test Pattern Generator), As camera sensor testing was not possible at that point. > > You cannot test bindings with TPG. It's impossible. > >> This is because Monaco-evk kit was not ready which can be used to enable sensor. >> >> These Bindings are complete in its own, If someone want to use TPG. > > No. You do not understand - they are not complete if you add new > properties to them! > > How bindings could be complete if you add now supplies!?!? > >> >> My latest update in these bindings are for camera sensor enablement which needs supplies too. >> >> Please let me know if this justification works to accept these bindings it its current form and add supplies as a separate patch. > > NAK. Read writing bindings doc. Or internal docs. > > Best regards, > Krzysztof @Vikram Could you send an updated dt-bindings with the supplies included ASAP as a v4 of this series ? The -supplies in your email here look fine 20250909114241.840842-5-quic_vikramsa@quicinc.com Otherwise we will have to drop this binding and the associated driver changes. --- bod
On 9/10/2025 2:12 PM, Bryan O'Donoghue wrote: > On 10/09/2025 08:42, Krzysztof Kozlowski wrote: >> On 10/09/2025 09:26, Vikram Sharma wrote: >>> >>> On 9/10/2025 12:35 PM, Krzysztof Kozlowski wrote: >>>> On 13/08/2025 07:37, Vikram Sharma wrote: >>>>> Add the compatible string "qcom,qcs8300-camss" to support the >>>>> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >>>>> >>>>> The QCS8300 platform provides: >>>>> - 2 x VFE (version 690), each with 3 RDI >>>>> - 5 x VFE Lite (version 690), each with 6 RDI >>>>> - 2 x CSID (version 690) >>>>> - 5 x CSID Lite (version 690) >>>>> - 3 x CSIPHY (version 690) >>>>> - 3 x TPG >>>>> >>>>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>>>> --- >>>>> .../bindings/media/qcom,qcs8300-camss.yaml | 336 >>>>> ++++++++++++++++++ >>>>> 1 file changed, 336 insertions(+) >>>> So it turns out this code is wrong and you already sent fixes for it. >>> >>> Hi Krzysztof, >>> Thanks for your comments. These bindings are tested with TPG (Test >>> Pattern Generator), As camera sensor testing was not possible at >>> that point. >> >> You cannot test bindings with TPG. It's impossible. >> >>> This is because Monaco-evk kit was not ready which can be used to >>> enable sensor. >>> >>> These Bindings are complete in its own, If someone want to use TPG. >> >> No. You do not understand - they are not complete if you add new >> properties to them! >> >> How bindings could be complete if you add now supplies!?!? Got it, Will post an updated version of this adding supplies and removing your RB. >> >>> >>> My latest update in these bindings are for camera sensor enablement >>> which needs supplies too. >>> >>> Please let me know if this justification works to accept these >>> bindings it its current form and add supplies as a separate patch. >> >> NAK. Read writing bindings doc. Or internal docs. >> >> Best regards, >> Krzysztof > > @Vikram > > Could you send an updated dt-bindings with the supplies included ASAP > as a v4 of this series ? on it, Will Remove your RB and send v3.1 for this patch > > The -supplies in your email here look fine > > 20250909114241.840842-5-quic_vikramsa@quicinc.com > > Otherwise we will have to drop this binding and the associated driver > changes. > > --- > bod Best regards, Vikram
On 13/08/2025 06:37, Vikram Sharma wrote:
> Add the compatible string "qcom,qcs8300-camss" to support the
> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform.
>
> The QCS8300 platform provides:
> - 2 x VFE (version 690), each with 3 RDI
> - 5 x VFE Lite (version 690), each with 6 RDI
> - 2 x CSID (version 690)
> - 5 x CSID Lite (version 690)
> - 3 x CSIPHY (version 690)
> - 3 x TPG
>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/media/qcom,qcs8300-camss.yaml | 336 ++++++++++++++++++
> 1 file changed, 336 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
> new file mode 100644
> index 000000000000..80a4540a22dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
> @@ -0,0 +1,336 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QCS8300 CAMSS ISP
> +
> +maintainers:
> + - Vikram Sharma <quic_vikramsa@quicinc.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,qcs8300-camss
> +
> + reg:
> + maxItems: 21
> +
> + reg-names:
> + items:
> + - const: csid_wrapper
> + - const: csid0
> + - const: csid1
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_lite2
> + - const: csid_lite3
> + - const: csid_lite4
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe_lite2
> + - const: vfe_lite3
> + - const: vfe_lite4
> +
> + clocks:
> + maxItems: 26
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: cpas_fast_ahb_clk
> + - const: cpas_vfe_lite
> + - const: cpas_vfe0
> + - const: cpas_vfe1
> + - const: csid
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy_rx
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: icp_ahb
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 20
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_lite2
> + - const: csid_lite3
> + - const: csid_lite4
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe_lite2
> + - const: vfe_lite3
> + - const: vfe_lite4
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_0
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + items:
> + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: top
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-2]+$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSIPHY 0-2.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@ac78000 {
> + compatible = "qcom,qcs8300-camss";
> +
> + reg = <0x0 0xac78000 0x0 0x1000>,
> + <0x0 0xac7a000 0x0 0x0f00>,
> + <0x0 0xac7c000 0x0 0x0f00>,
> + <0x0 0xac84000 0x0 0x0f00>,
> + <0x0 0xac88000 0x0 0x0f00>,
> + <0x0 0xac8c000 0x0 0x0f00>,
> + <0x0 0xac90000 0x0 0x0f00>,
> + <0x0 0xac94000 0x0 0x0f00>,
> + <0x0 0xac9c000 0x0 0x2000>,
> + <0x0 0xac9e000 0x0 0x2000>,
> + <0x0 0xaca0000 0x0 0x2000>,
> + <0x0 0xacac000 0x0 0x0400>,
> + <0x0 0xacad000 0x0 0x0400>,
> + <0x0 0xacae000 0x0 0x0400>,
> + <0x0 0xac4d000 0x0 0xd000>,
> + <0x0 0xac60000 0x0 0xd000>,
> + <0x0 0xac85000 0x0 0x0d00>,
> + <0x0 0xac89000 0x0 0x0d00>,
> + <0x0 0xac8d000 0x0 0x0d00>,
> + <0x0 0xac91000 0x0 0x0d00>,
> + <0x0 0xac95000 0x0 0x0d00>;
> + reg-names = "csid_wrapper",
> + "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "tpg0",
> + "tpg1",
> + "tpg2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe_lite2",
> + "vfe_lite3",
> + "vfe_lite4";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CORE_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_ICP_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "core_ahb",
> + "cpas_ahb",
> + "cpas_fast_ahb_clk",
> + "cpas_vfe_lite",
> + "cpas_vfe0",
> + "cpas_vfe1",
> + "csid",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy_rx",
> + "gcc_axi_hf",
> + "gcc_axi_sf",
> + "icp_ahb",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "tpg0",
> + "tpg1",
> + "tpg2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe_lite2",
> + "vfe_lite3",
> + "vfe_lite4";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_0";
> +
> + iommus = <&apps_smmu 0x2400 0x20>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "top";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add the compatible string "qcom,qcs8300-camss" to support the
Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform.
The QCS8300 platform provides:
- 2 x VFE (version 690), each with 3 RDI
- 5 x VFE Lite (version 690), each with 6 RDI
- 2 x CSID (version 690)
- 5 x CSID Lite (version 690)
- 3 x CSIPHY (version 690)
- 3 x TPG
Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
changes since v3:
- Adding supplies to enable camera sensor imx577 on monaco-evk.
link for camera sensor enablement chagges:
https://lore.kernel.org/all/20250909114241.840842-1-quic_vikramsa@quicinc.com/
- Dropped RB from Bryan and Krzysztof to review again.
---
.../bindings/media/qcom,qcs8300-camss.yaml | 349 ++++++++++++++++++
1 file changed, 349 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
new file mode 100644
index 000000000000..559db6d67f06
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
@@ -0,0 +1,349 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS8300 CAMSS ISP
+
+maintainers:
+ - Vikram Sharma <quic_vikramsa@quicinc.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,qcs8300-camss
+
+ reg:
+ maxItems: 21
+
+ reg-names:
+ items:
+ - const: csid_wrapper
+ - const: csid0
+ - const: csid1
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_lite2
+ - const: csid_lite3
+ - const: csid_lite4
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe_lite2
+ - const: vfe_lite3
+ - const: vfe_lite4
+
+ clocks:
+ maxItems: 26
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: cpas_fast_ahb_clk
+ - const: cpas_vfe_lite
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: csid
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: icp_ahb
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 20
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_lite2
+ - const: csid_lite3
+ - const: csid_lite4
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe_lite2
+ - const: vfe_lite3
+ - const: vfe_lite4
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: top
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-2]+$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 0-2.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - vdda-phy-supply
+ - vdda-pll-supply
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+ #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac78000 {
+ compatible = "qcom,qcs8300-camss";
+
+ reg = <0x0 0xac78000 0x0 0x1000>,
+ <0x0 0xac7a000 0x0 0x0f00>,
+ <0x0 0xac7c000 0x0 0x0f00>,
+ <0x0 0xac84000 0x0 0x0f00>,
+ <0x0 0xac88000 0x0 0x0f00>,
+ <0x0 0xac8c000 0x0 0x0f00>,
+ <0x0 0xac90000 0x0 0x0f00>,
+ <0x0 0xac94000 0x0 0x0f00>,
+ <0x0 0xac9c000 0x0 0x2000>,
+ <0x0 0xac9e000 0x0 0x2000>,
+ <0x0 0xaca0000 0x0 0x2000>,
+ <0x0 0xacac000 0x0 0x0400>,
+ <0x0 0xacad000 0x0 0x0400>,
+ <0x0 0xacae000 0x0 0x0400>,
+ <0x0 0xac4d000 0x0 0xd000>,
+ <0x0 0xac60000 0x0 0xd000>,
+ <0x0 0xac85000 0x0 0x0d00>,
+ <0x0 0xac89000 0x0 0x0d00>,
+ <0x0 0xac8d000 0x0 0x0d00>,
+ <0x0 0xac91000 0x0 0x0d00>,
+ <0x0 0xac95000 0x0 0x0d00>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb_clk",
+ "cpas_vfe_lite",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0";
+
+ iommus = <&apps_smmu 0x2400 0x20>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "top";
+
+ vdda-phy-supply = <&vreg_l4a_0p88>;
+ vdda-pll-supply = <&vreg_l1c_1p2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.25.1On 10/09/2025 12:49, Vikram Sharma wrote: > Add the compatible string "qcom,qcs8300-camss" to support the > Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. > > The QCS8300 platform provides: > - 2 x VFE (version 690), each with 3 RDI > - 5 x VFE Lite (version 690), each with 6 RDI > - 2 x CSID (version 690) > - 5 x CSID Lite (version 690) > - 3 x CSIPHY (version 690) > - 3 x TPG > > Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> > Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> Fast review only as courtesy to Bryan: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Next time patch which cannot be compared to previous version and has broken threading will end up at end of the queue. Best regards, Krzysztof
On 10/09/2025 15:07, Krzysztof Kozlowski wrote: > On 10/09/2025 12:49, Vikram Sharma wrote: >> Add the compatible string "qcom,qcs8300-camss" to support the >> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >> >> The QCS8300 platform provides: >> - 2 x VFE (version 690), each with 3 RDI >> - 5 x VFE Lite (version 690), each with 6 RDI >> - 2 x CSID (version 690) >> - 5 x CSID Lite (version 690) >> - 3 x CSIPHY (version 690) >> - 3 x TPG >> >> Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> >> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> > > > Fast review only as courtesy to Bryan: > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Next time patch which cannot be compared to previous version and has > broken threading will end up at end of the queue. > > Best regards, > Krzysztof Appreciated --- bod
On 10/09/2025 12:49, Vikram Sharma wrote: > Add the compatible string "qcom,qcs8300-camss" to support the > Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. > > The QCS8300 platform provides: > - 2 x VFE (version 690), each with 3 RDI > - 5 x VFE Lite (version 690), each with 6 RDI > - 2 x CSID (version 690) > - 5 x CSID Lite (version 690) > - 3 x CSIPHY (version 690) > - 3 x TPG > > Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> > Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> Do not attach (thread) your patchsets to some other threads (unrelated or older versions). This buries them deep in the mailbox and might interfere with applying entire sets. See also: https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L830 Please version your patches correctly, e.g. use b4 or git format-patch -vX, and add changelog in cover letter or under '---' of individual patches describing changes from previous version. What is v3.1? How to compare it? Try yourself: b4 diff '<20250910104915.1444669-1-quic_vikramsa@quicinc.com>' Grabbing thread from lore.kernel.org/all/20250910104915.1444669-1-quic_vikramsa@quicinc.com/t.mbox.gz Breaking thread to remove parents of 20250910104915.1444669-1-quic_vikramsa@quicinc.com --- Analyzing 2 messages in the thread Could not find lower series to compare against. Best regards, Krzysztof
On 9/10/25 1:38 PM, Krzysztof Kozlowski wrote: > On 10/09/2025 12:49, Vikram Sharma wrote: >> Add the compatible string "qcom,qcs8300-camss" to support the >> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >> >> The QCS8300 platform provides: >> - 2 x VFE (version 690), each with 3 RDI >> - 5 x VFE Lite (version 690), each with 6 RDI >> - 2 x CSID (version 690) >> - 5 x CSID Lite (version 690) >> - 3 x CSIPHY (version 690) >> - 3 x TPG >> >> Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> >> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> >> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > > Do not attach (thread) your patchsets to some other threads (unrelated > or older versions). This buries them deep in the mailbox and might > interfere with applying entire sets. See also: > https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L830 > > Please version your patches correctly, e.g. use b4 or git format-patch > -vX, and add changelog in cover letter or under '---' of individual > patches describing changes from previous version. > > What is v3.1? How to compare it? Try yourself: This is a weird invention that some media maintainers seem to promote.. As a b4 user, I would also like it to stop, as doing anything other than v(integer) will open the door for unlimited craziness Konrad
On Wed, Sep 10, 2025 at 02:25:30PM +0200, Konrad Dybcio wrote: > > Please version your patches correctly, e.g. use b4 or git format-patch > > -vX, and add changelog in cover letter or under '---' of individual > > patches describing changes from previous version. > > > > What is v3.1? How to compare it? Try yourself: > > This is a weird invention that some media maintainers seem to promote.. Please tell them to stop. Patch revisions are not supposed to follow any kind of semver. It's a new version of a patch and it should always be a simple full integer increment. > As a b4 user, I would also like it to stop, as doing anything other than > v(integer) will open the door for unlimited craziness To my knowledge, no tooling will do the right thing with that -- b4, patchwork, patchew, etc. It's needlessly complicating things. -K
On 10/09/2025 13:25, Konrad Dybcio wrote: > On 9/10/25 1:38 PM, Krzysztof Kozlowski wrote: >> On 10/09/2025 12:49, Vikram Sharma wrote: >>> Add the compatible string "qcom,qcs8300-camss" to support the >>> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. >>> >>> The QCS8300 platform provides: >>> - 2 x VFE (version 690), each with 3 RDI >>> - 5 x VFE Lite (version 690), each with 6 RDI >>> - 2 x CSID (version 690) >>> - 5 x CSID Lite (version 690) >>> - 3 x CSIPHY (version 690) >>> - 3 x TPG >>> >>> Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> >>> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> >>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >> >> Do not attach (thread) your patchsets to some other threads (unrelated >> or older versions). This buries them deep in the mailbox and might >> interfere with applying entire sets. See also: >> https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L830 >> >> Please version your patches correctly, e.g. use b4 or git format-patch >> -vX, and add changelog in cover letter or under '---' of individual >> patches describing changes from previous version. >> >> What is v3.1? How to compare it? Try yourself: > > This is a weird invention that some media maintainers seem to promote.. > > As a b4 user, I would also like it to stop, as doing anything other than > v(integer) will open the door for unlimited craziness > > Konrad This is from me, I asked Vikram for 3.1 instead of a whole new series. Anyway the fix isn't this patch its 20250909114241.840842-5-quic_vikramsa@quicinc.com --- bod
On 10/09/2025 11:49, Vikram Sharma wrote:
> Add the compatible string "qcom,qcs8300-camss" to support the
> Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform.
>
> The QCS8300 platform provides:
> - 2 x VFE (version 690), each with 3 RDI
> - 5 x VFE Lite (version 690), each with 6 RDI
> - 2 x CSID (version 690)
> - 5 x CSID Lite (version 690)
> - 3 x CSIPHY (version 690)
> - 3 x TPG
>
> Co-developed-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> changes since v3:
> - Adding supplies to enable camera sensor imx577 on monaco-evk.
> link for camera sensor enablement chagges:
> https://lore.kernel.org/all/20250909114241.840842-1-quic_vikramsa@quicinc.com/
> - Dropped RB from Bryan and Krzysztof to review again.
> ---
> .../bindings/media/qcom,qcs8300-camss.yaml | 349 ++++++++++++++++++
> 1 file changed, 349 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
> new file mode 100644
> index 000000000000..559db6d67f06
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml
> @@ -0,0 +1,349 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QCS8300 CAMSS ISP
> +
> +maintainers:
> + - Vikram Sharma <quic_vikramsa@quicinc.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,qcs8300-camss
> +
> + reg:
> + maxItems: 21
> +
> + reg-names:
> + items:
> + - const: csid_wrapper
> + - const: csid0
> + - const: csid1
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_lite2
> + - const: csid_lite3
> + - const: csid_lite4
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe_lite2
> + - const: vfe_lite3
> + - const: vfe_lite4
> +
> + clocks:
> + maxItems: 26
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: cpas_fast_ahb_clk
> + - const: cpas_vfe_lite
> + - const: cpas_vfe0
> + - const: cpas_vfe1
> + - const: csid
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy_rx
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: icp_ahb
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 20
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_lite2
> + - const: csid_lite3
> + - const: csid_lite4
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe_lite2
> + - const: vfe_lite3
> + - const: vfe_lite4
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_0
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + items:
> + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: top
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-2]+$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSIPHY 0-2.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - vdda-phy-supply
> + - vdda-pll-supply
> + - power-domain-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@ac78000 {
> + compatible = "qcom,qcs8300-camss";
> +
> + reg = <0x0 0xac78000 0x0 0x1000>,
> + <0x0 0xac7a000 0x0 0x0f00>,
> + <0x0 0xac7c000 0x0 0x0f00>,
> + <0x0 0xac84000 0x0 0x0f00>,
> + <0x0 0xac88000 0x0 0x0f00>,
> + <0x0 0xac8c000 0x0 0x0f00>,
> + <0x0 0xac90000 0x0 0x0f00>,
> + <0x0 0xac94000 0x0 0x0f00>,
> + <0x0 0xac9c000 0x0 0x2000>,
> + <0x0 0xac9e000 0x0 0x2000>,
> + <0x0 0xaca0000 0x0 0x2000>,
> + <0x0 0xacac000 0x0 0x0400>,
> + <0x0 0xacad000 0x0 0x0400>,
> + <0x0 0xacae000 0x0 0x0400>,
> + <0x0 0xac4d000 0x0 0xd000>,
> + <0x0 0xac60000 0x0 0xd000>,
> + <0x0 0xac85000 0x0 0x0d00>,
> + <0x0 0xac89000 0x0 0x0d00>,
> + <0x0 0xac8d000 0x0 0x0d00>,
> + <0x0 0xac91000 0x0 0x0d00>,
> + <0x0 0xac95000 0x0 0x0d00>;
> + reg-names = "csid_wrapper",
> + "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "tpg0",
> + "tpg1",
> + "tpg2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe_lite2",
> + "vfe_lite3",
> + "vfe_lite4";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CORE_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_ICP_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "core_ahb",
> + "cpas_ahb",
> + "cpas_fast_ahb_clk",
> + "cpas_vfe_lite",
> + "cpas_vfe0",
> + "cpas_vfe1",
> + "csid",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy_rx",
> + "gcc_axi_hf",
> + "gcc_axi_sf",
> + "icp_ahb",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "tpg0",
> + "tpg1",
> + "tpg2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe_lite2",
> + "vfe_lite3",
> + "vfe_lite4";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_0";
> +
> + iommus = <&apps_smmu 0x2400 0x20>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "top";
> +
> + vdda-phy-supply = <&vreg_l4a_0p88>;
> + vdda-pll-supply = <&vreg_l1c_1p2>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
OK LGTM thanks for your update.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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