On Mon, Aug 11, 2025 at 03:11:29PM GMT, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe0, board related gpios,
> PMIC regulators, etc for qcs8300-ride board.
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> index 8c166ead912c..e8e382db2b99 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> @@ -308,6 +308,23 @@ &iris {
> status = "okay";
> };
>
> +&pcie0 {
> + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
Since we have deprecated these properties in host bridge node recently, please
move these properties to PCI bridge node.
- Mani
> +
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + vdda-phy-supply = <&vreg_l6a>;
> + vdda-pll-supply = <&vreg_l5a>;
> +
> + status = "okay";
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
> @@ -348,6 +365,29 @@ ethernet0_mdio: ethernet0-mdio-pins {
> bias-pull-up;
> };
> };
> +
> + pcie0_default_state: pcie0-default-state {
> + wake-pins {
> + pins = "gpio0";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + clkreq-pins {
> + pins = "gpio1";
> + function = "pcie0_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-pins {
> + pins = "gpio2";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> };
>
> &uart7 {
> --
> 2.43.0
>
--
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