Like other platforms the sc7280 display clock controller provides a
couple of resets, add the defines to allow referring to them.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
---
 include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
index a4a692c20acfc954251fd1a1a59239ac62b20015..9f113f346be80b8a7815ffb17a6a6ce5e008f663 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
@@ -52,4 +52,8 @@
 /* DISP_CC power domains */
 #define DISP_CC_MDSS_CORE_GDSC				0
 
+/* DISPCC resets */
+#define DISP_CC_MDSS_CORE_BCR				0
+#define DISP_CC_MDSS_RSCC_BCR				1
+
 #endif

-- 
2.49.0

On 8/12/2025 8:41 AM, Bjorn Andersson wrote:
> Like other platforms the sc7280 display clock controller provides a
> couple of resets, add the defines to allow referring to them.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
>  include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
> index a4a692c20acfc954251fd1a1a59239ac62b20015..9f113f346be80b8a7815ffb17a6a6ce5e008f663 100644
> --- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
> +++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
> @@ -52,4 +52,8 @@
>  /* DISP_CC power domains */
>  #define DISP_CC_MDSS_CORE_GDSC				0
>  
> +/* DISPCC resets */
> +#define DISP_CC_MDSS_CORE_BCR				0
> +#define DISP_CC_MDSS_RSCC_BCR				1
> +
>  #endif
> 

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>

-- 
Thanks,
Taniya Das