From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the USB2 PHY controller for the Renesas RZ/T2H (r9a09g077) and
RZ/N2H (r9a09g087) SoCs. These SoCs share the same PHY block, which is
similar to the one on RZ/G2L but differs in clocks, resets, and register
bits. To account for these differences, a new compatible string
`renesas,usb2-phy-r9a09g077` is introduced.

The RZ/N2H SoC uses the same PHY as RZ/T2H, so it reuses the RZ/T2H
compatible string as a fallback.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v1->v2:
- Added Acked-by from Conor.
---
 .../bindings/phy/renesas,usb2-phy.yaml          | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index f45c5f039ae8..179cb4bfc424 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -44,6 +44,12 @@ properties:
           - const: renesas,usb2-phy-r9a09g056 # RZ/V2N
           - const: renesas,usb2-phy-r9a09g057
 
+      - const: renesas,usb2-phy-r9a09g077 # RZ/T2H
+
+      - items:
+          - const: renesas,usb2-phy-r9a09g087 # RZ/N2H
+          - const: renesas,usb2-phy-r9a09g077
+
   reg:
     maxItems: 1
 
@@ -120,6 +126,17 @@ allOf:
       required:
         - resets
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,usb2-phy-r9a09g077
+    then:
+      properties:
+        clocks:
+          minItems: 2
+        resets: false
+
 additionalProperties: false
 
 examples:
-- 
2.50.1

Hi Prabhakar,

On Fri, 8 Aug 2025 at 23:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document the USB2 PHY controller for the Renesas RZ/T2H (r9a09g077) and
> RZ/N2H (r9a09g087) SoCs. These SoCs share the same PHY block, which is
> similar to the one on RZ/G2L but differs in clocks, resets, and register
> bits. To account for these differences, a new compatible string
> `renesas,usb2-phy-r9a09g077` is introduced.
>
> The RZ/N2H SoC uses the same PHY as RZ/T2H, so it reuses the RZ/T2H
> compatible string as a fallback.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml

> @@ -120,6 +126,17 @@ allOf:
>        required:
>          - resets
>
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,usb2-phy-r9a09g077
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 2
> +        resets: false

By the time this hits upstream, you will probably have reset support
for RZ/T2H and RZ/N2H, so you just add renesas,usb2-phy-r9a09g077
to the conditional section above?

> +
>  additionalProperties: false
>
>  examples:

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Hi Geert,

Thank you for the review.

On Mon, Aug 11, 2025 at 2:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 8 Aug 2025 at 23:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document the USB2 PHY controller for the Renesas RZ/T2H (r9a09g077) and
> > RZ/N2H (r9a09g087) SoCs. These SoCs share the same PHY block, which is
> > similar to the one on RZ/G2L but differs in clocks, resets, and register
> > bits. To account for these differences, a new compatible string
> > `renesas,usb2-phy-r9a09g077` is introduced.
> >
> > The RZ/N2H SoC uses the same PHY as RZ/T2H, so it reuses the RZ/T2H
> > compatible string as a fallback.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
>
> > @@ -120,6 +126,17 @@ allOf:
> >        required:
> >          - resets
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,usb2-phy-r9a09g077
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 2
> > +        resets: false
>
> By the time this hits upstream, you will probably have reset support
> for RZ/T2H and RZ/N2H, so you just add renesas,usb2-phy-r9a09g077
> to the conditional section above?
>
But the above will still be true as MRCTLA/E/I/M register doesn't have
any bits to reset USB{PHY} or am I missing something?

Cheers,
Prabhakar

Hi Prabhakar,

On Mon, 11 Aug 2025 at 17:08, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Mon, Aug 11, 2025 at 2:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, 8 Aug 2025 at 23:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Document the USB2 PHY controller for the Renesas RZ/T2H (r9a09g077) and
> > > RZ/N2H (r9a09g087) SoCs. These SoCs share the same PHY block, which is
> > > similar to the one on RZ/G2L but differs in clocks, resets, and register
> > > bits. To account for these differences, a new compatible string
> > > `renesas,usb2-phy-r9a09g077` is introduced.
> > >
> > > The RZ/N2H SoC uses the same PHY as RZ/T2H, so it reuses the RZ/T2H
> > > compatible string as a fallback.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > Thanks for your patch!
> >
> > > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> >
> > > @@ -120,6 +126,17 @@ allOf:
> > >        required:
> > >          - resets
> > >
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            const: renesas,usb2-phy-r9a09g077
> > > +    then:
> > > +      properties:
> > > +        clocks:
> > > +          minItems: 2
> > > +        resets: false
> >
> > By the time this hits upstream, you will probably have reset support
> > for RZ/T2H and RZ/N2H, so you just add renesas,usb2-phy-r9a09g077
> > to the conditional section above?
> >
> But the above will still be true as MRCTLA/E/I/M register doesn't have
> any bits to reset USB{PHY} or am I missing something?

You are correct. I overlooked that some modules lack reset bits.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds