Add the vdpu381 Video Decoders to the rk3588-base devicetree.
The RK3588 based SoCs all embed 2 vdpu381 decoders.
This also adds the dedicated IOMMU controllers.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 70f03e68ba550..189f07c00089e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1252,6 +1252,70 @@ vepu121_3_mmu: iommu@fdbac800 {
#iommu-cells = <0>;
};
+ vdec0: video-codec@fdc38100 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdc38100 0x0 0x500>,
+ <0x0 0xfdc38000 0x0 0x100>,
+ <0x0 0xfdc38600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ iommus = <&vdec0_mmu>;
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&vdec0_sram>;
+ };
+
+ vdec0_mmu: iommu@fdc38700 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ #iommu-cells = <0>;
+ };
+
+ vdec1: video-codec@fdc40100 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdc40100 0x0 0x500>,
+ <0x0 0xfdc40000 0x0 0x100>,
+ <0x0 0xfdc40600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ iommus = <&vdec1_mmu>;
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&vdec1_sram>;
+ };
+
+ vdec1_mmu: iommu@fdc40700 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
@@ -3093,6 +3157,16 @@ system_sram2: sram@ff001000 {
ranges = <0x0 0x0 0xff001000 0xef000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ vdec0_sram: codec-sram@0 {
+ reg = <0x0 0x78000>;
+ pool;
+ };
+
+ vdec1_sram: codec-sram@78000 {
+ reg = <0x78000 0x77000>;
+ pool;
+ };
};
pinctrl: pinctrl {
--
2.50.1Hi, On Fri, Aug 08, 2025 at 03:36:01PM -0400, Detlev Casanova wrote: > Add the vdpu381 Video Decoders to the rk3588-base devicetree. > > The RK3588 based SoCs all embed 2 vdpu381 decoders. > This also adds the dedicated IOMMU controllers. Back in the VEPU121 enablement series[1] it had been decided to not expose multiple identical cores yet, because there is no infrastructure yet in the kernel to schedule multiple userland processes on multiple cores, or (more relevant for your usecase) to even combine two cores to reach 8K support. > > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > [snip] Thanks, [1] https://lore.kernel.org/all/20240618183816.77597-1-sebastian.reichel@collabora.com/ -- Link Mauve
Hi, On Sunday, 10 August 2025 15:22:54 EDT Link Mauve wrote: > Hi, > > On Fri, Aug 08, 2025 at 03:36:01PM -0400, Detlev Casanova wrote: > > Add the vdpu381 Video Decoders to the rk3588-base devicetree. > > > > The RK3588 based SoCs all embed 2 vdpu381 decoders. > > This also adds the dedicated IOMMU controllers. > > Back in the VEPU121 enablement series[1] it had been decided to not > expose multiple identical cores yet, because there is no infrastructure > yet in the kernel to schedule multiple userland processes on multiple > cores, or (more relevant for your usecase) to even combine two cores to > reach 8K support. That's right, but the device tree still defines the hardware as it is. The driver, however, will make sure that each instance after the first one is ignored (at least for now). > > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > > --- > > > > arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++ > > 1 file changed, 74 insertions(+) > > [snip] > > Thanks, > > [1] > https://lore.kernel.org/all/20240618183816.77597-1-sebastian.reichel@collab > ora.com/ Detlev.
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