From: Feng Chen <feng.chen@amlogic.com>
The Flash Controller is derived by adding an SPI path to the original
raw NAND controller. This controller supports two modes: raw mode and
SPI mode. The raw mode has already been implemented in the community,
and the SPI mode is described here.
Add bindings for Amlogic A113L2 SPI Flash Controller.
Signed-off-by: Feng Chen <feng.chen@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../devicetree/bindings/spi/amlogic,a4-spifc.yaml | 104 +++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml
new file mode 100644
index 000000000000..712a17a4b117
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI flash controller for Amlogic ARM SoCs
+
+maintainers:
+ - Liang Yang <liang.yang@amlogic.com>
+ - Feng Chen <feng.chen@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+description:
+ The Amlogic SPI flash controller is an extended version
+ of the Amlogic NAND flash controller. It supports SPI Nor
+ Flash and SPI NAND Flash(where the Host ECC HW engine could
+ be enabled).
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ const: amlogic,a4-spifc
+
+ reg:
+ items:
+ - description: core registers
+ - description: parent clk control registers
+
+ reg-names:
+ items:
+ - const: core
+ - const: pclk
+
+ clocks:
+ items:
+ - description: clock gate
+ - description: clock used for the controller
+ - description: clock used for the SPI bus
+
+ clock-names:
+ items:
+ - const: gate
+ - const: core
+ - const: device
+
+ interrupts:
+ maxItems: 1
+
+ amlogic,sfc-enable-random:
+ description: Enable data scrambling
+ type: boolean
+
+ amlogic,sfc-no-hwecc:
+ description: Disable ECC HW engine
+ type: boolean
+
+ amlogic,rx-adj:
+ description:
+ Adjust sample timing for RX, Sampling time
+ move later by 1 bus clock.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sfc0: spi@fe08d000 {
+ compatible = "amlogic,a4-spifc";
+ reg = <0xfe08d000 0x800>, <0xfe08c000 0x4>;
+ reg-names = "core", "pclk";
+ clocks = <&clkc_periphs 31>,
+ <&clkc_periphs 102>,
+ <&scmi_clk 13>;
+ clock-names = "gate", "core", "device";
+
+ pinctrl-0 = <&spiflash_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-engine = <&sfc0>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ };
+ };
--
2.37.1On Fri, Aug 08, 2025 at 10:00:34AM +0800, Xianwei Zhao wrote:
> From: Feng Chen <feng.chen@amlogic.com>
>
> The Flash Controller is derived by adding an SPI path to the original
> raw NAND controller. This controller supports two modes: raw mode and
> SPI mode. The raw mode has already been implemented in the community,
> and the SPI mode is described here.
>
Subject: drop doc, so just "Add Amlogic foo ..."
> Add bindings for Amlogic A113L2 SPI Flash Controller.
>
> Signed-off-by: Feng Chen <feng.chen@amlogic.com>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> .../devicetree/bindings/spi/amlogic,a4-spifc.yaml | 104 +++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml
> new file mode 100644
> index 000000000000..712a17a4b117
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SPI flash controller for Amlogic ARM SoCs
> +
> +maintainers:
> + - Liang Yang <liang.yang@amlogic.com>
> + - Feng Chen <feng.chen@amlogic.com>
> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
> +
> +description:
> + The Amlogic SPI flash controller is an extended version
> + of the Amlogic NAND flash controller. It supports SPI Nor
> + Flash and SPI NAND Flash(where the Host ECC HW engine could
> + be enabled).
Wrap at coding style, 80.
> +
> +allOf:
> + - $ref: /schemas/spi/spi-controller.yaml#
> +
> +properties:
> + compatible:
> + const: amlogic,a4-spifc
> +
> + reg:
> + items:
> + - description: core registers
> + - description: parent clk control registers
Why are you poking to parent node or to clock registers? This looks like
mixing up device address spaces.
> +
> + reg-names:
> + items:
> + - const: core
> + - const: pclk
> +
> + clocks:
> + items:
> + - description: clock gate
Are you sure this is separate clock input to this device?
> + - description: clock used for the controller
> + - description: clock used for the SPI bus
> +
> + clock-names:
> + items:
> + - const: gate
> + - const: core
> + - const: device
> +
> + interrupts:
> + maxItems: 1
> +
> + amlogic,sfc-enable-random:
> + description: Enable data scrambling
Why would this be a property of the board?
> + type: boolean
> +
> + amlogic,sfc-no-hwecc:
> + description: Disable ECC HW engine
Same question, why not having ECC always?
> + type: boolean
> +
> + amlogic,rx-adj:
> + description:
> + Adjust sample timing for RX, Sampling time
> + move later by 1 bus clock.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
> + default: 0
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + sfc0: spi@fe08d000 {
> + compatible = "amlogic,a4-spifc";
> + reg = <0xfe08d000 0x800>, <0xfe08c000 0x4>;
One register for the parent clock? This really does not look like part
of this device.
Best regards,
Krzysztof
Hi Krzysztof,
Thanks for your reply.
On 2025/8/8 16:03, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On Fri, Aug 08, 2025 at 10:00:34AM +0800, Xianwei Zhao wrote:
>> From: Feng Chen <feng.chen@amlogic.com>
>>
>> The Flash Controller is derived by adding an SPI path to the original
>> raw NAND controller. This controller supports two modes: raw mode and
>> SPI mode. The raw mode has already been implemented in the community,
>> and the SPI mode is described here.
>>
>
> Subject: drop doc, so just "Add Amlogic foo ..."
>
Will do.
>> Add bindings for Amlogic A113L2 SPI Flash Controller.
>>
>> Signed-off-by: Feng Chen <feng.chen@amlogic.com>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> .../devicetree/bindings/spi/amlogic,a4-spifc.yaml | 104 +++++++++++++++++++++
>> 1 file changed, 104 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml
>> new file mode 100644
>> index 000000000000..712a17a4b117
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml
>> @@ -0,0 +1,104 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: SPI flash controller for Amlogic ARM SoCs
>> +
>> +maintainers:
>> + - Liang Yang <liang.yang@amlogic.com>
>> + - Feng Chen <feng.chen@amlogic.com>
>> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
>> +
>> +description:
>> + The Amlogic SPI flash controller is an extended version
>> + of the Amlogic NAND flash controller. It supports SPI Nor
>> + Flash and SPI NAND Flash(where the Host ECC HW engine could
>> + be enabled).
>
> Wrap at coding style, 80.
>
Will do.
>> +
>> +allOf:
>> + - $ref: /schemas/spi/spi-controller.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: amlogic,a4-spifc
>> +
>> + reg:
>> + items:
>> + - description: core registers
>> + - description: parent clk control registers
>
> Why are you poking to parent node or to clock registers? This looks like
> mixing up device address spaces.
>
The SPIFC bus clock multiplexes EMMC modules, so the corresponding
frequency division register is also in EMMC module. The SPIFC and the
EMMC modules cannot be used simultaneously.
>> +
>> + reg-names:
>> + items:
>> + - const: core
>> + - const: pclk
>> +
>> + clocks:
>> + items:
>> + - description: clock gate
>
> Are you sure this is separate clock input to this device?
>
This clock is used by the APB interface to access the SPIFC registers.
>> + - description: clock used for the controller
>> + - description: clock used for the SPI bus
>> +
>> + clock-names:
>> + items:
>> + - const: gate
>> + - const: core
>> + - const: device
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + amlogic,sfc-enable-random:
>> + description: Enable data scrambling
>
> Why would this be a property of the board?
>
Will get rid of it.
>> + type: boolean
>> +
>> + amlogic,sfc-no-hwecc:
>> + description: Disable ECC HW engine
>
> Same question, why not having ECC always?
>
Will get rid of it.
>> + type: boolean
>> +
>> + amlogic,rx-adj:
>> + description:
>> + Adjust sample timing for RX, Sampling time
>> + move later by 1 bus clock.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + enum: [0, 1, 2, 3]
>> + default: 0
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + sfc0: spi@fe08d000 {
>> + compatible = "amlogic,a4-spifc";
>> + reg = <0xfe08d000 0x800>, <0xfe08c000 0x4>;
>
> One register for the parent clock? This really does not look like part
> of this device.
>
EMMC bus clock modules were reused.
> Best regards,
> Krzysztof
>
On 13/08/2025 08:13, Xianwei Zhao wrote: >>> +allOf: >>> + - $ref: /schemas/spi/spi-controller.yaml# >>> + >>> +properties: >>> + compatible: >>> + const: amlogic,a4-spifc >>> + >>> + reg: >>> + items: >>> + - description: core registers >>> + - description: parent clk control registers >> >> Why are you poking to parent node or to clock registers? This looks like >> mixing up device address spaces. >> > > The SPIFC bus clock multiplexes EMMC modules, so the corresponding > frequency division register is also in EMMC module. The SPIFC and the > EMMC modules cannot be used simultaneously. Then obviously you cannot put here EMMC or parent registers. It looks really like you miss proper hardware representation. > >>> + >>> + reg-names: >>> + items: >>> + - const: core >>> + - const: pclk >>> + >>> + clocks: >>> + items: >>> + - description: clock gate >> >> Are you sure this is separate clock input to this device? >> > > This clock is used by the APB interface to access the SPIFC registers. So APB clock? Best regards, Krzysztof
Hi Krzysztof,
Thanks for your reply.
On 2025/8/13 15:36, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 13/08/2025 08:13, Xianwei Zhao wrote:
>>>> +allOf:
>>>> + - $ref: /schemas/spi/spi-controller.yaml#
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: amlogic,a4-spifc
>>>> +
>>>> + reg:
>>>> + items:
>>>> + - description: core registers
>>>> + - description: parent clk control registers
>>>
>>> Why are you poking to parent node or to clock registers? This looks like
>>> mixing up device address spaces.
>>>
>>
>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding
>> frequency division register is also in EMMC module. The SPIFC and the
>> EMMC modules cannot be used simultaneously.
>
> Then obviously you cannot put here EMMC or parent registers.
>
> It looks really like you miss proper hardware representation.
>
It does seem a bit unusual. However, in our hardware design, EMMC and
SFC modules are integrated, and they share common resources such as the
clock and I/O pins .They are mutually exclusive.
Here, I'll modify the register description. Do you think it's feasible
description: EMMC clock divider control
>>
>>>> +
>>>> + reg-names:
>>>> + items:
>>>> + - const: core
>>>> + - const: pclk
>>>> +
>>>> + clocks:
>>>> + items:
>>>> + - description: clock gate
>>>
>>> Are you sure this is separate clock input to this device?
>>>
>>
>> This clock is used by the APB interface to access the SPIFC registers.
>
> So APB clock?
>
Yes. The APB clock serves as the source clock, but each device receives
it through an individual clock gating circuit.
I will modify the description of this clock
description: apb gate
>
>
> Best regards,
> Krzysztof
On 13/08/2025 11:34, Xianwei Zhao wrote: > Hi Krzysztof, > Thanks for your reply. > > On 2025/8/13 15:36, Krzysztof Kozlowski wrote: >> [ EXTERNAL EMAIL ] >> >> On 13/08/2025 08:13, Xianwei Zhao wrote: >>>>> +allOf: >>>>> + - $ref: /schemas/spi/spi-controller.yaml# >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + const: amlogic,a4-spifc >>>>> + >>>>> + reg: >>>>> + items: >>>>> + - description: core registers >>>>> + - description: parent clk control registers >>>> >>>> Why are you poking to parent node or to clock registers? This looks like >>>> mixing up device address spaces. >>>> >>> >>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding >>> frequency division register is also in EMMC module. The SPIFC and the >>> EMMC modules cannot be used simultaneously. >> >> Then obviously you cannot put here EMMC or parent registers. >> >> It looks really like you miss proper hardware representation. >> > > It does seem a bit unusual. However, in our hardware design, EMMC and > SFC modules are integrated, and they share common resources such as the > clock and I/O pins .They are mutually exclusive. > How did you express it in DT? This looks similar to serial engines and such are not implemented independently. > Here, I'll modify the register description. Do you think it's feasible No, because it changes nothing... Clock provider pokes clock divider registers. Not clock consumer. Best regards, Krzysztof
Hi Krzysztof,
Thanks for your reply.
On 2025/8/14 00:19, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 13/08/2025 11:34, Xianwei Zhao wrote:
>> Hi Krzysztof,
>> Thanks for your reply.
>>
>> On 2025/8/13 15:36, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 13/08/2025 08:13, Xianwei Zhao wrote:
>>>>>> +allOf:
>>>>>> + - $ref: /schemas/spi/spi-controller.yaml#
>>>>>> +
>>>>>> +properties:
>>>>>> + compatible:
>>>>>> + const: amlogic,a4-spifc
>>>>>> +
>>>>>> + reg:
>>>>>> + items:
>>>>>> + - description: core registers
>>>>>> + - description: parent clk control registers
>>>>>
>>>>> Why are you poking to parent node or to clock registers? This looks like
>>>>> mixing up device address spaces.
>>>>>
>>>>
>>>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding
>>>> frequency division register is also in EMMC module. The SPIFC and the
>>>> EMMC modules cannot be used simultaneously.
>>>
>>> Then obviously you cannot put here EMMC or parent registers.
>>>
>>> It looks really like you miss proper hardware representation.
>>>
>>
>> It does seem a bit unusual. However, in our hardware design, EMMC and
>> SFC modules are integrated, and they share common resources such as the
>> clock and I/O pins .They are mutually exclusive.
>>
>
> How did you express it in DT? This looks similar to serial engines and
> such are not implemented independently.
>
The hardware design provides this clock for both modules — EMMC and
SPIFC. A control bit (bit 31: Cfg_NAND, where 0 = Port C only, 1 = NAND)
is used to determine which module uses the clock.
It's not that NAND is using EMMC’s resources; rather, the configuration
register controlling this selection is located within the EMMC module,
which makes the setup appear somewhat unusual.
In the device tree (DT), I'll just refer directly to the clock frequency
division control register.
If I don't describe it here, then when SPIFC needs to operate, EMMC will
be disabled. In that case, I won’t be able to access the corresponding
clock division setting, which means SPIFC won't be able to function either.
>> Here, I'll modify the register description. Do you think it's feasible
>
> No, because it changes nothing... Clock provider pokes clock divider
> registers. Not clock consumer.
>
> Best regards,
> Krzysztof
On 14/08/2025 08:38, Xianwei Zhao wrote: > Hi Krzysztof, > Thanks for your reply. > > On 2025/8/14 00:19, Krzysztof Kozlowski wrote: >> [ EXTERNAL EMAIL ] >> >> On 13/08/2025 11:34, Xianwei Zhao wrote: >>> Hi Krzysztof, >>> Thanks for your reply. >>> >>> On 2025/8/13 15:36, Krzysztof Kozlowski wrote: >>>> [ EXTERNAL EMAIL ] >>>> >>>> On 13/08/2025 08:13, Xianwei Zhao wrote: >>>>>>> +allOf: >>>>>>> + - $ref: /schemas/spi/spi-controller.yaml# >>>>>>> + >>>>>>> +properties: >>>>>>> + compatible: >>>>>>> + const: amlogic,a4-spifc >>>>>>> + >>>>>>> + reg: >>>>>>> + items: >>>>>>> + - description: core registers >>>>>>> + - description: parent clk control registers >>>>>> >>>>>> Why are you poking to parent node or to clock registers? This looks like >>>>>> mixing up device address spaces. >>>>>> >>>>> >>>>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding >>>>> frequency division register is also in EMMC module. The SPIFC and the >>>>> EMMC modules cannot be used simultaneously. >>>> >>>> Then obviously you cannot put here EMMC or parent registers. >>>> >>>> It looks really like you miss proper hardware representation. >>>> >>> >>> It does seem a bit unusual. However, in our hardware design, EMMC and >>> SFC modules are integrated, and they share common resources such as the >>> clock and I/O pins .They are mutually exclusive. >>> >> >> How did you express it in DT? This looks similar to serial engines and >> such are not implemented independently. >> > > The hardware design provides this clock for both modules — EMMC and > SPIFC. A control bit (bit 31: Cfg_NAND, where 0 = Port C only, 1 = NAND) > is used to determine which module uses the clock. > > It's not that NAND is using EMMC’s resources; rather, the configuration > register controlling this selection is located within the EMMC module, > which makes the setup appear somewhat unusual. No, how did you express in DT that they are mutually exclusive? > > In the device tree (DT), I'll just refer directly to the clock frequency > division control register. This does not solve the exclusive usage... Best regards, Krzysztof
Hi Krzysztof,
Thanks for your reply.
On 2025/8/17 15:20, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 14/08/2025 08:38, Xianwei Zhao wrote:
>> Hi Krzysztof,
>> Thanks for your reply.
>>
>> On 2025/8/14 00:19, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 13/08/2025 11:34, Xianwei Zhao wrote:
>>>> Hi Krzysztof,
>>>> Thanks for your reply.
>>>>
>>>> On 2025/8/13 15:36, Krzysztof Kozlowski wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On 13/08/2025 08:13, Xianwei Zhao wrote:
>>>>>>>> +allOf:
>>>>>>>> + - $ref: /schemas/spi/spi-controller.yaml#
>>>>>>>> +
>>>>>>>> +properties:
>>>>>>>> + compatible:
>>>>>>>> + const: amlogic,a4-spifc
>>>>>>>> +
>>>>>>>> + reg:
>>>>>>>> + items:
>>>>>>>> + - description: core registers
>>>>>>>> + - description: parent clk control registers
>>>>>>>
>>>>>>> Why are you poking to parent node or to clock registers? This looks like
>>>>>>> mixing up device address spaces.
>>>>>>>
>>>>>>
>>>>>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding
>>>>>> frequency division register is also in EMMC module. The SPIFC and the
>>>>>> EMMC modules cannot be used simultaneously.
>>>>>
>>>>> Then obviously you cannot put here EMMC or parent registers.
>>>>>
>>>>> It looks really like you miss proper hardware representation.
>>>>>
>>>>
>>>> It does seem a bit unusual. However, in our hardware design, EMMC and
>>>> SFC modules are integrated, and they share common resources such as the
>>>> clock and I/O pins .They are mutually exclusive.
>>>>
>>>
>>> How did you express it in DT? This looks similar to serial engines and
>>> such are not implemented independently.
>>>
>>
>> The hardware design provides this clock for both modules — EMMC and
>> SPIFC. A control bit (bit 31: Cfg_NAND, where 0 = Port C only, 1 = NAND)
>> is used to determine which module uses the clock.
>>
>> It's not that NAND is using EMMC’s resources; rather, the configuration
>> register controlling this selection is located within the EMMC module,
>> which makes the setup appear somewhat unusual.
>
> No, how did you express in DT that they are mutually exclusive?
>
I will remove this part of the register description. The clock
implementation will be placed in the common module. The SFC is only used
as a consumer for the clock.
>>
>> In the device tree (DT), I'll just refer directly to the clock frequency
>> division control register.
>
> This does not solve the exclusive usage...
>
>
> Best regards,
> Krzysztof
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