On 09/08/2025 03:35, Jessica Zhang wrote:
> The HPD state status is the last 3 bits, not 4 bits of the
> HPD_INT_STATUS register.
Then the mask is incorrect too. Also, I'd suggest using 'most
significant' instead of 'last'. The latter one might be confusing.
>
> Fix the bit shift macro so that the correct bits are returned in
> msm_dp_aux_is_link_connected().
>
> Fixes: 19e52bcb27c2 ("drm/msm/dp: return correct connection status after suspend")
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/dp/dp_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
> index 7c44d4e2cf13..b851efc132ea 100644
> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> @@ -69,7 +69,7 @@
> #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004)
> #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008)
> #define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F)
> -#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C)
> +#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1D)
>
> #define REG_DP_DP_HPD_INT_MASK (0x0000000C)
> #define DP_DP_HPD_PLUG_INT_MASK (0x00000001)
>
--
With best wishes
Dmitry