On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external
shared reset in the RCC. Add the reset to both m_can nodes.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
arch/arm/boot/dts/st/stm32mp153.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi
index 4640dafb1598..92794b942ab2 100644
--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
@@ -40,6 +40,7 @@ m_can1: can@4400e000 {
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
+ resets = <&rcc FDCAN_R>;
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
access-controllers = <&etzpc 62>;
status = "disabled";
@@ -54,6 +55,7 @@ m_can2: can@4400f000 {
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
+ resets = <&rcc FDCAN_R>;
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
access-controllers = <&etzpc 62>;
status = "disabled";
--
2.47.2
Hi Marc On 8/7/25 08:09, Marc Kleine-Budde wrote: > On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external > shared reset in the RCC. Add the reset to both m_can nodes. > > Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> > --- > arch/arm/boot/dts/st/stm32mp153.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi > index 4640dafb1598..92794b942ab2 100644 > --- a/arch/arm/boot/dts/st/stm32mp153.dtsi > +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi > @@ -40,6 +40,7 @@ m_can1: can@4400e000 { > interrupt-names = "int0", "int1"; > clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; > clock-names = "hclk", "cclk"; > + resets = <&rcc FDCAN_R>; > bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; > access-controllers = <&etzpc 62>; > status = "disabled"; > @@ -54,6 +55,7 @@ m_can2: can@4400f000 { > interrupt-names = "int0", "int1"; > clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; > clock-names = "hclk", "cclk"; > + resets = <&rcc FDCAN_R>; > bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; > access-controllers = <&etzpc 62>; > status = "disabled"; > How those reset are handled at driver side ? regards alex
On 03.09.2025 15:10:42, Alexandre TORGUE wrote: > Hi Marc > > On 8/7/25 08:09, Marc Kleine-Budde wrote: > > On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external > > shared reset in the RCC. Add the reset to both m_can nodes. > > > > Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> > > --- > > arch/arm/boot/dts/st/stm32mp153.dtsi | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi > > index 4640dafb1598..92794b942ab2 100644 > > --- a/arch/arm/boot/dts/st/stm32mp153.dtsi > > +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi > > @@ -40,6 +40,7 @@ m_can1: can@4400e000 { > > interrupt-names = "int0", "int1"; > > clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; > > clock-names = "hclk", "cclk"; > > + resets = <&rcc FDCAN_R>; > > bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; > > access-controllers = <&etzpc 62>; > > status = "disabled"; > > @@ -54,6 +55,7 @@ m_can2: can@4400f000 { > > interrupt-names = "int0", "int1"; > > clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; > > clock-names = "hclk", "cclk"; > > + resets = <&rcc FDCAN_R>; > > bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; > > access-controllers = <&etzpc 62>; > > status = "disabled"; > > > > How those reset are handled at driver side ? I've created a patch that adds a shared reset to the m_can driver: | https://lore.kernel.org/all/20250812-m_can-fix-state-handling-v1-7-b739e06c0a3b@pengutronix.de/ The reset is de-asserted during probe and when the interface does up, otherwise it asserted. This way the IP gets reset only when both interfaces are down. regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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