From: Jason Tian <jason@os.amperecomputing.com>
The ARM processor CPER record was added in UEFI v2.6 and remained
unchanged up to v2.10.
Yet, the original arm_event trace code added by
e9279e83ad1f ("trace, ras: add ARM processor error trace event")
is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not
exporting any information from tables N.17 to N.29 of the record.
This is not enough for the user to be able to figure out what has
exactly happened or to take appropriate action.
According to the UEFI v2.9 specification chapter N2.4.4, the ARM
processor error section includes:
- several (ERR_INFO_NUM) ARM processor error information structures
(Tables N.17 to N.20);
- several (CONTEXT_INFO_NUM) ARM processor context information
structures (Tables N.21 to N.29);
- several vendor specific error information structures. The
size is given by Section Length minus the size of the other
fields.
In addition, it also exports two fields that are parsed by the GHES
driver when firmware reports it, e.g.:
- error severity
- CPU logical index
Report all of these information to userspace via a the ARM tracepoint so
that userspace can properly record the error and take decisions related
to CPU core isolation according to error severity and other info.
The updated ARM trace event now contains the following fields:
====================================== =============================
UEFI field on table N.16 ARM Processor trace fields
====================================== =============================
Validation handled when filling data for
affinity MPIDR and running
state.
ERR_INFO_NUM pei_len
CONTEXT_INFO_NUM ctx_len
Section Length indirectly reported by
pei_len, ctx_len and oem_len
Error affinity level affinity
MPIDR_EL1 mpidr
MIDR_EL1 midr
Running State running_state
PSCI State psci_state
Processor Error Information Structure pei_err - count at pei_len
Processor Context ctx_err- count at ctx_len
Vendor Specific Error Info oem - count at oem_len
====================================== =============================
It should be noted that decoding of tables N.17 to N.29, if needed, will
be handled in userspace. That gives more flexibility, as there won't be
any need to flood the kernel with micro-architecture specific error
decoding.
Also, decoding the other fields require a complex logic, and should be
done for each of the several values inside the record field. So, let
userspace daemons like rasdaemon decode them, parsing such tables and
having vendor-specific micro-architecture-specific decoders.
[mchehab: modified description, solved merge conflicts and fixed coding style]
Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
Co-developed-by: Jason Tian <jason@os.amperecomputing.com>
Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Shiju Jose <shiju.jose@huawei.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-section
---
drivers/acpi/apei/ghes.c | 11 ++++-------
drivers/ras/ras.c | 41 +++++++++++++++++++++++++++++++++++++++--
include/linux/ras.h | 16 +++++++++++++---
include/ras/ras_event.h | 48 +++++++++++++++++++++++++++++++++++++++++++-----
4 files changed, 99 insertions(+), 17 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index f0584ccad451915a2679c17f2367461c141663c5..99e25553fc1320b2306efb751e12f2377c86878a 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -527,7 +527,7 @@ static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata,
}
static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata,
- int sev, bool sync)
+ int sev, bool sync)
{
struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);
int flags = sync ? MF_ACTION_REQUIRED : 0;
@@ -535,9 +535,8 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata,
int sec_sev, i;
char *p;
- log_arm_hw_error(err);
-
sec_sev = ghes_severity(gdata->error_severity);
+ log_arm_hw_error(err, sec_sev);
if (sev != GHES_SEV_RECOVERABLE || sec_sev != GHES_SEV_RECOVERABLE)
return false;
@@ -870,11 +869,9 @@ static bool ghes_do_proc(struct ghes *ghes,
arch_apei_report_mem_error(sev, mem_err);
queued = ghes_handle_memory_failure(gdata, sev, sync);
- }
- else if (guid_equal(sec_type, &CPER_SEC_PCIE)) {
+ } else if (guid_equal(sec_type, &CPER_SEC_PCIE)) {
ghes_handle_aer(gdata);
- }
- else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) {
+ } else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) {
queued = ghes_handle_arm_hw_error(gdata, sev, sync);
} else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) {
struct cxl_cper_sec_prot_err *prot_err = acpi_hest_get_payload(gdata);
diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c
index a6e4792a1b2e9239f44f29102a7cc058d64b93ef..179b1744df71ee1eac28718628d550075c480cd5 100644
--- a/drivers/ras/ras.c
+++ b/drivers/ras/ras.c
@@ -52,9 +52,46 @@ void log_non_standard_event(const guid_t *sec_type, const guid_t *fru_id,
trace_non_standard_event(sec_type, fru_id, fru_text, sev, err, len);
}
-void log_arm_hw_error(struct cper_sec_proc_arm *err)
+void log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev)
{
- trace_arm_event(err);
+ struct cper_arm_err_info *err_info;
+ struct cper_arm_ctx_info *ctx_info;
+ u8 *ven_err_data;
+ u32 ctx_len = 0;
+ int n, sz, cpu;
+ s32 vsei_len;
+ u32 pei_len;
+ u8 *pei_err;
+ u8 *ctx_err;
+
+ pei_len = sizeof(struct cper_arm_err_info) * err->err_info_num;
+ pei_err = (u8 *)err + sizeof(struct cper_sec_proc_arm);
+
+ err_info = (struct cper_arm_err_info *)(err + 1);
+ ctx_info = (struct cper_arm_ctx_info *)(err_info + err->err_info_num);
+ ctx_err = (u8 *)ctx_info;
+
+ for (n = 0; n < err->context_info_num; n++) {
+ sz = sizeof(struct cper_arm_ctx_info) + ctx_info->size;
+ ctx_info = (struct cper_arm_ctx_info *)((long)ctx_info + sz);
+ ctx_len += sz;
+ }
+
+ vsei_len = err->section_length - (sizeof(struct cper_sec_proc_arm) + pei_len + ctx_len);
+ if (vsei_len < 0) {
+ pr_warn(FW_BUG "section length: %d\n", err->section_length);
+ pr_warn(FW_BUG "section length is too small\n");
+ pr_warn(FW_BUG "firmware-generated error record is incorrect\n");
+ vsei_len = 0;
+ }
+ ven_err_data = (u8 *)ctx_info;
+
+ cpu = GET_LOGICAL_INDEX(err->mpidr);
+ if (cpu < 0)
+ cpu = -1;
+
+ trace_arm_event(err, pei_err, pei_len, ctx_err, ctx_len,
+ ven_err_data, (u32)vsei_len, sev, cpu);
}
static int __init ras_init(void)
diff --git a/include/linux/ras.h b/include/linux/ras.h
index a64182bc72ad3f2b430c53c7a9e23e798a1c1fbe..468941bfe855f6a1e3471245d98df5ffb362385b 100644
--- a/include/linux/ras.h
+++ b/include/linux/ras.h
@@ -24,8 +24,7 @@ int __init parse_cec_param(char *str);
void log_non_standard_event(const guid_t *sec_type,
const guid_t *fru_id, const char *fru_text,
const u8 sev, const u8 *err, const u32 len);
-void log_arm_hw_error(struct cper_sec_proc_arm *err);
-
+void log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev);
#else
static inline void
log_non_standard_event(const guid_t *sec_type,
@@ -33,7 +32,7 @@ log_non_standard_event(const guid_t *sec_type,
const u8 sev, const u8 *err, const u32 len)
{ return; }
static inline void
-log_arm_hw_error(struct cper_sec_proc_arm *err) { return; }
+log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev) { return; }
#endif
struct atl_err {
@@ -53,4 +52,15 @@ static inline unsigned long
amd_convert_umc_mca_addr_to_sys_addr(struct atl_err *err) { return -EINVAL; }
#endif /* CONFIG_AMD_ATL */
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+#include <asm/smp_plat.h>
+/*
+ * Include ARM-specific SMP header which provides a function mapping mpidr to
+ * CPU logical index.
+ */
+#define GET_LOGICAL_INDEX(mpidr) get_logical_index(mpidr & MPIDR_HWID_BITMASK)
+#else
+#define GET_LOGICAL_INDEX(mpidr) -EINVAL
+#endif /* CONFIG_ARM || CONFIG_ARM64 */
+
#endif /* __RAS_H__ */
diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
index 14c9f943d53fb6cbadeef3f4b13e61470f0b5dee..a6b7ac0adaff9dfeab05a0c75ed359930ae04479 100644
--- a/include/ras/ras_event.h
+++ b/include/ras/ras_event.h
@@ -168,11 +168,24 @@ TRACE_EVENT(mc_event,
* This event is generated when hardware detects an ARM processor error
* has occurred. UEFI 2.6 spec section N.2.4.4.
*/
+#define APEIL "ARM Processor Err Info data len"
+#define APEID "ARM Processor Err Info raw data"
+#define APECIL "ARM Processor Err Context Info data len"
+#define APECID "ARM Processor Err Context Info raw data"
+#define VSEIL "Vendor Specific Err Info data len"
+#define VSEID "Vendor Specific Err Info raw data"
TRACE_EVENT(arm_event,
- TP_PROTO(const struct cper_sec_proc_arm *proc),
+ TP_PROTO(const struct cper_sec_proc_arm *proc, const u8 *pei_err,
+ const u32 pei_len,
+ const u8 *ctx_err,
+ const u32 ctx_len,
+ const u8 *oem,
+ const u32 oem_len,
+ u8 sev,
+ int cpu),
- TP_ARGS(proc),
+ TP_ARGS(proc, pei_err, pei_len, ctx_err, ctx_len, oem, oem_len, sev, cpu),
TP_STRUCT__entry(
__field(u64, mpidr)
@@ -180,6 +193,14 @@ TRACE_EVENT(arm_event,
__field(u32, running_state)
__field(u32, psci_state)
__field(u8, affinity)
+ __field(u32, pei_len)
+ __dynamic_array(u8, pei_buf, pei_len)
+ __field(u32, ctx_len)
+ __dynamic_array(u8, ctx_buf, ctx_len)
+ __field(u32, oem_len)
+ __dynamic_array(u8, oem_buf, oem_len)
+ __field(u8, sev)
+ __field(int, cpu)
),
TP_fast_assign(
@@ -199,12 +220,29 @@ TRACE_EVENT(arm_event,
__entry->running_state = ~0;
__entry->psci_state = ~0;
}
+ __entry->pei_len = pei_len;
+ memcpy(__get_dynamic_array(pei_buf), pei_err, pei_len);
+ __entry->ctx_len = ctx_len;
+ memcpy(__get_dynamic_array(ctx_buf), ctx_err, ctx_len);
+ __entry->oem_len = oem_len;
+ memcpy(__get_dynamic_array(oem_buf), oem, oem_len);
+ __entry->sev = sev;
+ __entry->cpu = cpu;
),
- TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; "
- "running state: %d; PSCI state: %d",
+ TP_printk("cpu: %d; error: %d; affinity level: %d; MPIDR: %016llx; MIDR: %016llx; "
+ "running state: %d; PSCI state: %d; "
+ "%s: %d; %s: %s; %s: %d; %s: %s; %s: %d; %s: %s",
+ __entry->cpu,
+ __entry->sev,
__entry->affinity, __entry->mpidr, __entry->midr,
- __entry->running_state, __entry->psci_state)
+ __entry->running_state, __entry->psci_state,
+ APEIL, __entry->pei_len, APEID,
+ __print_hex(__get_dynamic_array(pei_buf), __entry->pei_len),
+ APECIL, __entry->ctx_len, APECID,
+ __print_hex(__get_dynamic_array(ctx_buf), __entry->ctx_len),
+ VSEIL, __entry->oem_len, VSEID,
+ __print_hex(__get_dynamic_array(oem_buf), __entry->oem_len))
);
/*
--
2.50.0On Tue, 05 Aug 2025 11:35:38 -0700
Daniel Ferguson <danielf@os.amperecomputing.com> wrote:
> From: Jason Tian <jason@os.amperecomputing.com>
>
> The ARM processor CPER record was added in UEFI v2.6 and remained
> unchanged up to v2.10.
>
> Yet, the original arm_event trace code added by
>
> e9279e83ad1f ("trace, ras: add ARM processor error trace event")
>
> is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not
> exporting any information from tables N.17 to N.29 of the record.
>
> This is not enough for the user to be able to figure out what has
> exactly happened or to take appropriate action.
>
> According to the UEFI v2.9 specification chapter N2.4.4, the ARM
> processor error section includes:
>
> - several (ERR_INFO_NUM) ARM processor error information structures
> (Tables N.17 to N.20);
> - several (CONTEXT_INFO_NUM) ARM processor context information
> structures (Tables N.21 to N.29);
> - several vendor specific error information structures. The
> size is given by Section Length minus the size of the other
> fields.
>
> In addition, it also exports two fields that are parsed by the GHES
> driver when firmware reports it, e.g.:
>
> - error severity
> - CPU logical index
>
> Report all of these information to userspace via a the ARM tracepoint so
> that userspace can properly record the error and take decisions related
> to CPU core isolation according to error severity and other info.
>
> The updated ARM trace event now contains the following fields:
>
> ====================================== =============================
> UEFI field on table N.16 ARM Processor trace fields
> ====================================== =============================
> Validation handled when filling data for
> affinity MPIDR and running
> state.
> ERR_INFO_NUM pei_len
> CONTEXT_INFO_NUM ctx_len
> Section Length indirectly reported by
> pei_len, ctx_len and oem_len
> Error affinity level affinity
> MPIDR_EL1 mpidr
> MIDR_EL1 midr
> Running State running_state
> PSCI State psci_state
> Processor Error Information Structure pei_err - count at pei_len
> Processor Context ctx_err- count at ctx_len
> Vendor Specific Error Info oem - count at oem_len
> ====================================== =============================
>
> It should be noted that decoding of tables N.17 to N.29, if needed, will
> be handled in userspace. That gives more flexibility, as there won't be
> any need to flood the kernel with micro-architecture specific error
> decoding.
>
> Also, decoding the other fields require a complex logic, and should be
> done for each of the several values inside the record field. So, let
> userspace daemons like rasdaemon decode them, parsing such tables and
> having vendor-specific micro-architecture-specific decoders.
>
> [mchehab: modified description, solved merge conflicts and fixed coding style]
>
> Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
>
Fixes tag is part of the main tag block so no blank line here.
There are at least some scripts running on the kernel tree that trip
up on this (and one that moans at the submitter ;)
I'd also add something to explain the SoB sequence for the curious.
> Co-developed-by: Jason Tian <jason@os.amperecomputing.com>
Jason's the Author, so shouldn't have a Co-dev tag.
There is some info on this in
https://docs.kernel.org/process/submitting-patches.html
> Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
> Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
> Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
> Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
As person submitting I'd normally expect your SoB last.
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
I guess this is because Mauro posted an earlier version in which
case this is arguably correct, but likely to confuse.
For cases like this I add comments.
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Tested-by: Shiju Jose <shiju.jose@huawei.com>
> Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
> Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-section
A couple of trivial things inline.
> diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c
> index a6e4792a1b2e9239f44f29102a7cc058d64b93ef..179b1744df71ee1eac28718628d550075c480cd5 100644
> --- a/drivers/ras/ras.c
> +++ b/drivers/ras/ras.c
> @@ -52,9 +52,46 @@ void log_non_standard_event(const guid_t *sec_type, const guid_t *fru_id,
> trace_non_standard_event(sec_type, fru_id, fru_text, sev, err, len);
> }
>
> -void log_arm_hw_error(struct cper_sec_proc_arm *err)
> +void log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev)
> {
> - trace_arm_event(err);
> + struct cper_arm_err_info *err_info;
> + struct cper_arm_ctx_info *ctx_info;
> + u8 *ven_err_data;
> + u32 ctx_len = 0;
> + int n, sz, cpu;
> + s32 vsei_len;
> + u32 pei_len;
> + u8 *pei_err;
> + u8 *ctx_err;
Maybe combine the two u8 *
> +
> + pei_len = sizeof(struct cper_arm_err_info) * err->err_info_num;
> + pei_err = (u8 *)err + sizeof(struct cper_sec_proc_arm);
pei_err = (u8 *)(err + 1);
Which is the same as err_info. Setting one to the other will make that
relationship more obvious if we do need to keep them both around.
(Similar to the ctx_err = (u8 *)ctx_info; below)
> +
> + err_info = (struct cper_arm_err_info *)(err + 1);
> + ctx_info = (struct cper_arm_ctx_info *)(err_info + err->err_info_num);
> + ctx_err = (u8 *)ctx_info;
> +
> + for (n = 0; n < err->context_info_num; n++) {
> + sz = sizeof(struct cper_arm_ctx_info) + ctx_info->size;
> + ctx_info = (struct cper_arm_ctx_info *)((long)ctx_info + sz);
> + ctx_len += sz;
> + }
> +
> + vsei_len = err->section_length - (sizeof(struct cper_sec_proc_arm) + pei_len + ctx_len);
> + if (vsei_len < 0) {
> + pr_warn(FW_BUG "section length: %d\n", err->section_length);
> + pr_warn(FW_BUG "section length is too small\n");
> + pr_warn(FW_BUG "firmware-generated error record is incorrect\n");
> + vsei_len = 0;
> + }
> + ven_err_data = (u8 *)ctx_info;
> +
> + cpu = GET_LOGICAL_INDEX(err->mpidr);
> + if (cpu < 0)
> + cpu = -1;
> +
> + trace_arm_event(err, pei_err, pei_len, ctx_err, ctx_len,
> + ven_err_data, (u32)vsei_len, sev, cpu);
> }
> diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
> index 14c9f943d53fb6cbadeef3f4b13e61470f0b5dee..a6b7ac0adaff9dfeab05a0c75ed359930ae04479 100644
> --- a/include/ras/ras_event.h
> +++ b/include/ras/ras_event.h
> @@ -168,11 +168,24 @@ TRACE_EVENT(mc_event,
> * This event is generated when hardware detects an ARM processor error
> * has occurred. UEFI 2.6 spec section N.2.4.4.
> */
> +#define APEIL "ARM Processor Err Info data len"
> +#define APEID "ARM Processor Err Info raw data"
> +#define APECIL "ARM Processor Err Context Info data len"
> +#define APECID "ARM Processor Err Context Info raw data"
> +#define VSEIL "Vendor Specific Err Info data len"
> +#define VSEID "Vendor Specific Err Info raw data"
> TRACE_EVENT(arm_event,
>
> - TP_PROTO(const struct cper_sec_proc_arm *proc),
> + TP_PROTO(const struct cper_sec_proc_arm *proc, const u8 *pei_err,
> + const u32 pei_len,
Trivial but this is an odd bit of wrapping to have two items
on first line, but then only one on later lines. Also additional
indent seems unusual and isn't matched by the first few things I looked
at in this file. So should be under the c of const (one space I think
rather than a tab).
> + const u8 *ctx_err,
> + const u32 ctx_len,
> + const u8 *oem,
> + const u32 oem_len,
> + u8 sev,
> + int cpu),
>
Em Fri, 8 Aug 2025 16:22:09 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> escreveu:
> On Tue, 05 Aug 2025 11:35:38 -0700
> Daniel Ferguson <danielf@os.amperecomputing.com> wrote:
>
> > From: Jason Tian <jason@os.amperecomputing.com>
> >
> > The ARM processor CPER record was added in UEFI v2.6 and remained
> > unchanged up to v2.10.
> >
> > Yet, the original arm_event trace code added by
> >
> > e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> >
> > is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not
> > exporting any information from tables N.17 to N.29 of the record.
> >
> > This is not enough for the user to be able to figure out what has
> > exactly happened or to take appropriate action.
> >
> > According to the UEFI v2.9 specification chapter N2.4.4, the ARM
> > processor error section includes:
> >
> > - several (ERR_INFO_NUM) ARM processor error information structures
> > (Tables N.17 to N.20);
> > - several (CONTEXT_INFO_NUM) ARM processor context information
> > structures (Tables N.21 to N.29);
> > - several vendor specific error information structures. The
> > size is given by Section Length minus the size of the other
> > fields.
> >
> > In addition, it also exports two fields that are parsed by the GHES
> > driver when firmware reports it, e.g.:
> >
> > - error severity
> > - CPU logical index
> >
> > Report all of these information to userspace via a the ARM tracepoint so
> > that userspace can properly record the error and take decisions related
> > to CPU core isolation according to error severity and other info.
> >
> > The updated ARM trace event now contains the following fields:
> >
> > ====================================== =============================
> > UEFI field on table N.16 ARM Processor trace fields
> > ====================================== =============================
> > Validation handled when filling data for
> > affinity MPIDR and running
> > state.
> > ERR_INFO_NUM pei_len
> > CONTEXT_INFO_NUM ctx_len
> > Section Length indirectly reported by
> > pei_len, ctx_len and oem_len
> > Error affinity level affinity
> > MPIDR_EL1 mpidr
> > MIDR_EL1 midr
> > Running State running_state
> > PSCI State psci_state
> > Processor Error Information Structure pei_err - count at pei_len
> > Processor Context ctx_err- count at ctx_len
> > Vendor Specific Error Info oem - count at oem_len
> > ====================================== =============================
> >
> > It should be noted that decoding of tables N.17 to N.29, if needed, will
> > be handled in userspace. That gives more flexibility, as there won't be
> > any need to flood the kernel with micro-architecture specific error
> > decoding.
> >
> > Also, decoding the other fields require a complex logic, and should be
> > done for each of the several values inside the record field. So, let
> > userspace daemons like rasdaemon decode them, parsing such tables and
> > having vendor-specific micro-architecture-specific decoders.
> >
> > [mchehab: modified description, solved merge conflicts and fixed coding style]
> >
> > Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> >
>
> Fixes tag is part of the main tag block so no blank line here.
> There are at least some scripts running on the kernel tree that trip
> up on this (and one that moans at the submitter ;)
>
> I'd also add something to explain the SoB sequence for the curious.
>
> > Co-developed-by: Jason Tian <jason@os.amperecomputing.com>
>
> Jason's the Author, so shouldn't have a Co-dev tag.
> There is some info on this in
> https://docs.kernel.org/process/submitting-patches.html
My understanding is that all co-authors shall have co-developed-by
and SoB. Anyway, doesn't matter much in practice, I guess.
>
> > Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
> > Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
> > Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
> > Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> > Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
>
> As person submitting I'd normally expect your SoB last.
>
> > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
>
> I guess this is because Mauro posted an earlier version in which
> case this is arguably correct, but likely to confuse.
> For cases like this I add comments.
If the patch is identical, and it is just a resubmission,
I would keep the original order.
Otherwise, if Daniel did some changes at the code (except for a
trivial rebase stuff), better to move his co-developed-by/SoB to
the end, eventually adding:
[Daniel: <did something>] before the custody chain block.
Thanks,
Mauro
On Sat, 9 Aug 2025 17:55:19 +0200
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
> Em Fri, 8 Aug 2025 16:22:09 +0100
> Jonathan Cameron <Jonathan.Cameron@huawei.com> escreveu:
>
> > On Tue, 05 Aug 2025 11:35:38 -0700
> > Daniel Ferguson <danielf@os.amperecomputing.com> wrote:
> >
> > > From: Jason Tian <jason@os.amperecomputing.com>
> > >
> > > The ARM processor CPER record was added in UEFI v2.6 and remained
> > > unchanged up to v2.10.
> > >
> > > Yet, the original arm_event trace code added by
> > >
> > > e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> > >
> > > is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not
> > > exporting any information from tables N.17 to N.29 of the record.
> > >
> > > This is not enough for the user to be able to figure out what has
> > > exactly happened or to take appropriate action.
> > >
> > > According to the UEFI v2.9 specification chapter N2.4.4, the ARM
> > > processor error section includes:
> > >
> > > - several (ERR_INFO_NUM) ARM processor error information structures
> > > (Tables N.17 to N.20);
> > > - several (CONTEXT_INFO_NUM) ARM processor context information
> > > structures (Tables N.21 to N.29);
> > > - several vendor specific error information structures. The
> > > size is given by Section Length minus the size of the other
> > > fields.
> > >
> > > In addition, it also exports two fields that are parsed by the GHES
> > > driver when firmware reports it, e.g.:
> > >
> > > - error severity
> > > - CPU logical index
> > >
> > > Report all of these information to userspace via a the ARM tracepoint so
> > > that userspace can properly record the error and take decisions related
> > > to CPU core isolation according to error severity and other info.
> > >
> > > The updated ARM trace event now contains the following fields:
> > >
> > > ====================================== =============================
> > > UEFI field on table N.16 ARM Processor trace fields
> > > ====================================== =============================
> > > Validation handled when filling data for
> > > affinity MPIDR and running
> > > state.
> > > ERR_INFO_NUM pei_len
> > > CONTEXT_INFO_NUM ctx_len
> > > Section Length indirectly reported by
> > > pei_len, ctx_len and oem_len
> > > Error affinity level affinity
> > > MPIDR_EL1 mpidr
> > > MIDR_EL1 midr
> > > Running State running_state
> > > PSCI State psci_state
> > > Processor Error Information Structure pei_err - count at pei_len
> > > Processor Context ctx_err- count at ctx_len
> > > Vendor Specific Error Info oem - count at oem_len
> > > ====================================== =============================
> > >
> > > It should be noted that decoding of tables N.17 to N.29, if needed, will
> > > be handled in userspace. That gives more flexibility, as there won't be
> > > any need to flood the kernel with micro-architecture specific error
> > > decoding.
> > >
> > > Also, decoding the other fields require a complex logic, and should be
> > > done for each of the several values inside the record field. So, let
> > > userspace daemons like rasdaemon decode them, parsing such tables and
> > > having vendor-specific micro-architecture-specific decoders.
> > >
> > > [mchehab: modified description, solved merge conflicts and fixed coding style]
> > >
> > > Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> > >
> >
> > Fixes tag is part of the main tag block so no blank line here.
> > There are at least some scripts running on the kernel tree that trip
> > up on this (and one that moans at the submitter ;)
> >
> > I'd also add something to explain the SoB sequence for the curious.
> >
> > > Co-developed-by: Jason Tian <jason@os.amperecomputing.com>
> >
> > Jason's the Author, so shouldn't have a Co-dev tag.
> > There is some info on this in
> > https://docs.kernel.org/process/submitting-patches.html
>
> My understanding is that all co-authors shall have co-developed-by
> and SoB. Anyway, doesn't matter much in practice, I guess.
Nope. In the description the docs say "in addition to the author
attribute in the From: tag" There are also examples where there
isn't a Co-dev for the From author including the subtle question of
ordering if someone else posts that patch.
I have a vague recollection one of the scripts checking linux-next
might moan about this.
>
> >
> > > Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
> > > Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
> > > Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
> > > Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> > > Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> >
> > As person submitting I'd normally expect your SoB last.
> >
> > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> >
> > I guess this is because Mauro posted an earlier version in which
> > case this is arguably correct, but likely to confuse.
> > For cases like this I add comments.
>
> If the patch is identical, and it is just a resubmission,
> I would keep the original order.
>
> Otherwise, if Daniel did some changes at the code (except for a
> trivial rebase stuff), better to move his co-developed-by/SoB to
> the end, eventually adding:
>
> [Daniel: <did something>] before the custody chain block.
Docs are clear that sender of the patch must be last SoB.
That's also checked by the some of the tag block check scripts
I think. There's an example of exactly this case in the in the
submitting-patches.rst file (last one in the section that talks
about Co-developed-by.
For meaning I don't care that much, but keeping to the rigid
rules in that doc makes it easier for scripts to check for the
more important stuff like whether all necessary SoB are there.
Jonathan
>
> Thanks,
> Mauro
>
On 8/11/2025 3:52 AM, Jonathan Cameron wrote:
> On Sat, 9 Aug 2025 17:55:19 +0200
> Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
>
>> Em Fri, 8 Aug 2025 16:22:09 +0100
>> Jonathan Cameron <Jonathan.Cameron@huawei.com> escreveu:
>>
>>> On Tue, 05 Aug 2025 11:35:38 -0700
>>> Daniel Ferguson <danielf@os.amperecomputing.com> wrote:
>>>
>>>> From: Jason Tian <jason@os.amperecomputing.com>
>>>>
>>>> The ARM processor CPER record was added in UEFI v2.6 and remained
>>>> unchanged up to v2.10.
>>>>
>>>> Yet, the original arm_event trace code added by
>>>>
>>>> e9279e83ad1f ("trace, ras: add ARM processor error trace event")
>>>>
>>>> is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not
>>>> exporting any information from tables N.17 to N.29 of the record.
>>>>
>>>> This is not enough for the user to be able to figure out what has
>>>> exactly happened or to take appropriate action.
>>>>
>>>> According to the UEFI v2.9 specification chapter N2.4.4, the ARM
>>>> processor error section includes:
>>>>
>>>> - several (ERR_INFO_NUM) ARM processor error information structures
>>>> (Tables N.17 to N.20);
>>>> - several (CONTEXT_INFO_NUM) ARM processor context information
>>>> structures (Tables N.21 to N.29);
>>>> - several vendor specific error information structures. The
>>>> size is given by Section Length minus the size of the other
>>>> fields.
>>>>
>>>> In addition, it also exports two fields that are parsed by the GHES
>>>> driver when firmware reports it, e.g.:
>>>>
>>>> - error severity
>>>> - CPU logical index
>>>>
>>>> Report all of these information to userspace via a the ARM tracepoint so
>>>> that userspace can properly record the error and take decisions related
>>>> to CPU core isolation according to error severity and other info.
>>>>
>>>> The updated ARM trace event now contains the following fields:
>>>>
>>>> ====================================== =============================
>>>> UEFI field on table N.16 ARM Processor trace fields
>>>> ====================================== =============================
>>>> Validation handled when filling data for
>>>> affinity MPIDR and running
>>>> state.
>>>> ERR_INFO_NUM pei_len
>>>> CONTEXT_INFO_NUM ctx_len
>>>> Section Length indirectly reported by
>>>> pei_len, ctx_len and oem_len
>>>> Error affinity level affinity
>>>> MPIDR_EL1 mpidr
>>>> MIDR_EL1 midr
>>>> Running State running_state
>>>> PSCI State psci_state
>>>> Processor Error Information Structure pei_err - count at pei_len
>>>> Processor Context ctx_err- count at ctx_len
>>>> Vendor Specific Error Info oem - count at oem_len
>>>> ====================================== =============================
>>>>
>>>> It should be noted that decoding of tables N.17 to N.29, if needed, will
>>>> be handled in userspace. That gives more flexibility, as there won't be
>>>> any need to flood the kernel with micro-architecture specific error
>>>> decoding.
>>>>
>>>> Also, decoding the other fields require a complex logic, and should be
>>>> done for each of the several values inside the record field. So, let
>>>> userspace daemons like rasdaemon decode them, parsing such tables and
>>>> having vendor-specific micro-architecture-specific decoders.
>>>>
>>>> [mchehab: modified description, solved merge conflicts and fixed coding style]
>>>>
>>>> Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
>>>>
>>>
>>> Fixes tag is part of the main tag block so no blank line here.
>>> There are at least some scripts running on the kernel tree that trip
>>> up on this (and one that moans at the submitter ;)
>>>
>>> I'd also add something to explain the SoB sequence for the curious.
>>>
>>>> Co-developed-by: Jason Tian <jason@os.amperecomputing.com>
>>>
>>> Jason's the Author, so shouldn't have a Co-dev tag.
>>> There is some info on this in
>>> https://docs.kernel.org/process/submitting-patches.html
>>
>> My understanding is that all co-authors shall have co-developed-by
>> and SoB. Anyway, doesn't matter much in practice, I guess.
>
> Nope. In the description the docs say "in addition to the author
> attribute in the From: tag" There are also examples where there
> isn't a Co-dev for the From author including the subtle question of
> ordering if someone else posts that patch.
>
> I have a vague recollection one of the scripts checking linux-next
> might moan about this.
>
>>
>>>
>>>> Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
>>>> Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
>>>> Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
>>>> Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
>>>> Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
>>>
>>> As person submitting I'd normally expect your SoB last.
>>>
>>>> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
>>>
>>> I guess this is because Mauro posted an earlier version in which
>>> case this is arguably correct, but likely to confuse.
>>> For cases like this I add comments.
>>
>> If the patch is identical, and it is just a resubmission,
>> I would keep the original order.
>>
>> Otherwise, if Daniel did some changes at the code (except for a
>> trivial rebase stuff), better to move his co-developed-by/SoB to
>> the end, eventually adding:
>>
>> [Daniel: <did something>] before the custody chain block.
>
> Docs are clear that sender of the patch must be last SoB.
> That's also checked by the some of the tag block check scripts
> I think. There's an example of exactly this case in the in the
> submitting-patches.rst file (last one in the section that talks
> about Co-developed-by.
>
> For meaning I don't care that much, but keeping to the rigid
> rules in that doc makes it easier for scripts to check for the
> more important stuff like whether all necessary SoB are there.
>
> Jonathan
>
Just to make sure I get this right...
I will move my SoB and my Co-developed-by after any other SoB's in the tag
block. As a result, I do not need to provide an explanation in this case,
because there is nothing curious remaining ? Or should I still add comments
indicating why I rearranged the tag block ?
Based on your feedback, I'm intending to organize the tag block to look like this:
Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Shiju Jose <shiju.jose@huawei.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
Link:
https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-section
Is that satisfactory?
Thank you,
Daniel
>>
>> Thanks,
>> Mauro
>>
>
On Mon, 11 Aug 2025 15:37:18 -0700
Daniel Ferguson <danielf@os.amperecomputing.com> wrote:
> On 8/11/2025 3:52 AM, Jonathan Cameron wrote:
> > On Sat, 9 Aug 2025 17:55:19 +0200
> > Mauro Carvalho Chehab <mchehab+huawei@kernel.org> wrote:
> >
> >> Em Fri, 8 Aug 2025 16:22:09 +0100
> >> Jonathan Cameron <Jonathan.Cameron@huawei.com> escreveu:
> >>
> >>> On Tue, 05 Aug 2025 11:35:38 -0700
> >>> Daniel Ferguson <danielf@os.amperecomputing.com> wrote:
> >>>
> >>>> From: Jason Tian <jason@os.amperecomputing.com>
> >>>>
> >>>> The ARM processor CPER record was added in UEFI v2.6 and remained
> >>>> unchanged up to v2.10.
> >>>>
> >>>> Yet, the original arm_event trace code added by
> >>>>
> >>>> e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> >>>>
> >>>> is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not
> >>>> exporting any information from tables N.17 to N.29 of the record.
> >>>>
> >>>> This is not enough for the user to be able to figure out what has
> >>>> exactly happened or to take appropriate action.
> >>>>
> >>>> According to the UEFI v2.9 specification chapter N2.4.4, the ARM
> >>>> processor error section includes:
> >>>>
> >>>> - several (ERR_INFO_NUM) ARM processor error information structures
> >>>> (Tables N.17 to N.20);
> >>>> - several (CONTEXT_INFO_NUM) ARM processor context information
> >>>> structures (Tables N.21 to N.29);
> >>>> - several vendor specific error information structures. The
> >>>> size is given by Section Length minus the size of the other
> >>>> fields.
> >>>>
> >>>> In addition, it also exports two fields that are parsed by the GHES
> >>>> driver when firmware reports it, e.g.:
> >>>>
> >>>> - error severity
> >>>> - CPU logical index
> >>>>
> >>>> Report all of these information to userspace via a the ARM tracepoint so
> >>>> that userspace can properly record the error and take decisions related
> >>>> to CPU core isolation according to error severity and other info.
> >>>>
> >>>> The updated ARM trace event now contains the following fields:
> >>>>
> >>>> ====================================== =============================
> >>>> UEFI field on table N.16 ARM Processor trace fields
> >>>> ====================================== =============================
> >>>> Validation handled when filling data for
> >>>> affinity MPIDR and running
> >>>> state.
> >>>> ERR_INFO_NUM pei_len
> >>>> CONTEXT_INFO_NUM ctx_len
> >>>> Section Length indirectly reported by
> >>>> pei_len, ctx_len and oem_len
> >>>> Error affinity level affinity
> >>>> MPIDR_EL1 mpidr
> >>>> MIDR_EL1 midr
> >>>> Running State running_state
> >>>> PSCI State psci_state
> >>>> Processor Error Information Structure pei_err - count at pei_len
> >>>> Processor Context ctx_err- count at ctx_len
> >>>> Vendor Specific Error Info oem - count at oem_len
> >>>> ====================================== =============================
> >>>>
> >>>> It should be noted that decoding of tables N.17 to N.29, if needed, will
> >>>> be handled in userspace. That gives more flexibility, as there won't be
> >>>> any need to flood the kernel with micro-architecture specific error
> >>>> decoding.
> >>>>
> >>>> Also, decoding the other fields require a complex logic, and should be
> >>>> done for each of the several values inside the record field. So, let
> >>>> userspace daemons like rasdaemon decode them, parsing such tables and
> >>>> having vendor-specific micro-architecture-specific decoders.
> >>>>
> >>>> [mchehab: modified description, solved merge conflicts and fixed coding style]
> >>>>
> >>>> Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> >>>>
> >>>
> >>> Fixes tag is part of the main tag block so no blank line here.
> >>> There are at least some scripts running on the kernel tree that trip
> >>> up on this (and one that moans at the submitter ;)
> >>>
> >>> I'd also add something to explain the SoB sequence for the curious.
> >>>
> >>>> Co-developed-by: Jason Tian <jason@os.amperecomputing.com>
> >>>
> >>> Jason's the Author, so shouldn't have a Co-dev tag.
> >>> There is some info on this in
> >>> https://docs.kernel.org/process/submitting-patches.html
> >>
> >> My understanding is that all co-authors shall have co-developed-by
> >> and SoB. Anyway, doesn't matter much in practice, I guess.
> >
> > Nope. In the description the docs say "in addition to the author
> > attribute in the From: tag" There are also examples where there
> > isn't a Co-dev for the From author including the subtle question of
> > ordering if someone else posts that patch.
> >
> > I have a vague recollection one of the scripts checking linux-next
> > might moan about this.
> >
> >>
> >>>
> >>>> Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
> >>>> Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
> >>>> Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
> >>>> Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> >>>> Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> >>>
> >>> As person submitting I'd normally expect your SoB last.
> >>>
> >>>> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> >>>
> >>> I guess this is because Mauro posted an earlier version in which
> >>> case this is arguably correct, but likely to confuse.
> >>> For cases like this I add comments.
> >>
> >> If the patch is identical, and it is just a resubmission,
> >> I would keep the original order.
> >>
> >> Otherwise, if Daniel did some changes at the code (except for a
> >> trivial rebase stuff), better to move his co-developed-by/SoB to
> >> the end, eventually adding:
> >>
> >> [Daniel: <did something>] before the custody chain block.
> >
> > Docs are clear that sender of the patch must be last SoB.
> > That's also checked by the some of the tag block check scripts
> > I think. There's an example of exactly this case in the in the
> > submitting-patches.rst file (last one in the section that talks
> > about Co-developed-by.
> >
> > For meaning I don't care that much, but keeping to the rigid
> > rules in that doc makes it easier for scripts to check for the
> > more important stuff like whether all necessary SoB are there.
> >
> > Jonathan
> >
>
> Just to make sure I get this right...
>
> I will move my SoB and my Co-developed-by after any other SoB's in the tag
> block. As a result, I do not need to provide an explanation in this case,
> because there is nothing curious remaining ? Or should I still add comments
> indicating why I rearranged the tag block ?
>
> Based on your feedback, I'm intending to organize the tag block to look like this:
>
> Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
> Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
> Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Tested-by: Shiju Jose <shiju.jose@huawei.com>
> Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
> Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event")
> Link:
> https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-section
>
>
> Is that satisfactory?
The SoB from Mauro is still out of the normal pattern which
tends to happen only when things are bouncing between different submitters.
So I'd still add a comment and keep that after you Codev/SoB.
#1 [mchehab: modified description, solved merge conflicts and fixed coding style
in version 3.]
Signed-off-by: Jason Tian <jason@os.amperecomputing.com>
Co-developed-by: Shengwei Luo <luoshengwei@huawei.com>
Signed-off-by: Shengwei Luo <luoshengwei@huawei.com>
Co-developed-by: Daniel Ferguson <danielf@os.amperecomputing.com>
Signed-off-by: Daniel Ferguson <danielf@os.amperecomputing.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> # 1
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Shiju Jose <shiju.jose@huawei.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-section
Or something along those lines
Jonathan
>
> Thank you,
> Daniel
>
> >>
> >> Thanks,
> >> Mauro
> >>
> >
>
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