Add WAKE# gpio which is needed to bring PCIe device state
from D3cold to D0.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 1 +
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 10c152ac03c874df5f1dc386d9079d3db1c55362..a4d85772f86955ad061433b138581fa9d81110a4 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -810,6 +810,7 @@ &mdss_edp_phy {
&pcieport1 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index 60b3cf50ea1d61dd5e8b573b5f1c6faa1c291eee..5e73060771329cade097bf1a71056a456a7937d7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -477,6 +477,7 @@ &pcie1 {
&pcieport1 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
&pm8350c_pwm {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 0b0212b670797a364d7f0e7a458fc73245fff8db..240513774612fb2bfcdb951e5a5a77c49f49eb82 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -418,6 +418,7 @@ &lpass_va_macro {
&pcieport1 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
--
2.34.1
On Fri, Aug 01, 2025 at 04:29:42PM +0530, Krishna Chaitanya Chundru wrote: > Add WAKE# gpio which is needed to bring PCIe device state > from D3cold to D0. > What tree did you base this on? None of these boards has pcieport1 defined in the upstream kernel. Regards, Bjorn > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 1 + > arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 10c152ac03c874df5f1dc386d9079d3db1c55362..a4d85772f86955ad061433b138581fa9d81110a4 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -810,6 +810,7 @@ &mdss_edp_phy { > > &pcieport1 { > reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; > }; > > &pcie1 { > diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi > index 60b3cf50ea1d61dd5e8b573b5f1c6faa1c291eee..5e73060771329cade097bf1a71056a456a7937d7 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi > @@ -477,6 +477,7 @@ &pcie1 { > > &pcieport1 { > reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; > }; > > &pm8350c_pwm { > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > index 0b0212b670797a364d7f0e7a458fc73245fff8db..240513774612fb2bfcdb951e5a5a77c49f49eb82 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > @@ -418,6 +418,7 @@ &lpass_va_macro { > > &pcieport1 { > reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; > }; > > &pcie1 { > > -- > 2.34.1 >
On 8/11/2025 10:06 PM, Bjorn Andersson wrote: > On Fri, Aug 01, 2025 at 04:29:42PM +0530, Krishna Chaitanya Chundru wrote: >> Add WAKE# gpio which is needed to bring PCIe device state >> from D3cold to D0. >> > > What tree did you base this on? None of these boards has pcieport1 > defined in the upstream kernel. > Sorry I forgot to add dependencies to dependencies to one more series. I will add the dependencies in the next series. - Krishna Chaitanya. > Regards, > Bjorn > >> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >> --- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 1 + >> arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + >> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 + >> 3 files changed, 3 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> index 10c152ac03c874df5f1dc386d9079d3db1c55362..a4d85772f86955ad061433b138581fa9d81110a4 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> @@ -810,6 +810,7 @@ &mdss_edp_phy { >> >> &pcieport1 { >> reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; >> + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; >> }; >> >> &pcie1 { >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi >> index 60b3cf50ea1d61dd5e8b573b5f1c6faa1c291eee..5e73060771329cade097bf1a71056a456a7937d7 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi >> @@ -477,6 +477,7 @@ &pcie1 { >> >> &pcieport1 { >> reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; >> + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; >> }; >> >> &pm8350c_pwm { >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> index 0b0212b670797a364d7f0e7a458fc73245fff8db..240513774612fb2bfcdb951e5a5a77c49f49eb82 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> @@ -418,6 +418,7 @@ &lpass_va_macro { >> >> &pcieport1 { >> reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; >> + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; >> }; >> >> &pcie1 { >> >> -- >> 2.34.1 >>
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