.../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 167 +++++++++++++++++++ .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 ++++++++++++++++++++ .../devicetree/bindings/ufs/qcom,ufs-common.yaml | 67 ++++++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 185 ++++----------------- 4 files changed, 446 insertions(+), 151 deletions(-)
Changes in v2: - Patch #2: rename subject to SC7180 and include SC7180 as well. SC7180 has one clock less. - New Patch #3: Split SM8650 and SM8750 to their own file, because these are first variants with MCQ. Add also MCQ address space, to fully document the hardware. - Link to v1: https://lore.kernel.org/r/20250730-dt-bindings-ufs-qcom-v1-0-4cec9ff202dc@linaro.org Description: The binding for Qualcomm SoC UFS controllers grew and it will grow further. It already includes several conditionals, partially for difference in handling encryption block (ICE, either as phandle or as IO address space) but it will further grow for MCQ. See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com The SM8650 is first SoC coming with MCQ, which was missing in the binding. Document this as well. Best regards, Krzysztof --- Krzysztof Kozlowski (3): dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml dt-bindings: ufs: qcom: Split SC7180 and similar dt-bindings: ufs: qcom: Split SM8650 and similar .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 167 +++++++++++++++++++ .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 ++++++++++++++++++++ .../devicetree/bindings/ufs/qcom,ufs-common.yaml | 67 ++++++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 185 ++++----------------- 4 files changed, 446 insertions(+), 151 deletions(-) --- base-commit: d7af19298454ed155f5cf67201a70f5cf836c842 change-id: 20250730-dt-bindings-ufs-qcom-980795ebd0aa Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Krzysztof, > The binding for Qualcomm SoC UFS controllers grew and it will grow > further. It already includes several conditionals, partially for > difference in handling encryption block (ICE, either as phandle or as > IO address space) but it will further grow for MCQ. Which tree did you intend to route this through? -- Martin K. Petersen
On 06/08/2025 04:37, Martin K. Petersen wrote: > > Krzysztof, > >> The binding for Qualcomm SoC UFS controllers grew and it will grow >> further. It already includes several conditionals, partially for >> difference in handling encryption block (ICE, either as phandle or as >> IO address space) but it will further grow for MCQ. > > Which tree did you intend to route this through? These are bindings, so please take them via UFS tree. Just like with every other driver or bindings patch. Best regards, Krzysztof
On 06/08/2025 07:58, Krzysztof Kozlowski wrote: > On 06/08/2025 04:37, Martin K. Petersen wrote: >> >> Krzysztof, >> >>> The binding for Qualcomm SoC UFS controllers grew and it will grow >>> further. It already includes several conditionals, partially for >>> difference in handling encryption block (ICE, either as phandle or as >>> IO address space) but it will further grow for MCQ. >> >> Which tree did you intend to route this through? > > > These are bindings, so please take them via UFS tree. Just like with > every other driver or bindings patch. Hi Martin, Did my answer reach you? Any questions about applying/merging? Best regards, Krzysztof
Krzysztof, > Did my answer reach you? Any questions about applying/merging? I'm planning on merging the series later today. -- Martin K. Petersen
Krzysztof, > The binding for Qualcomm SoC UFS controllers grew and it will grow > further. It already includes several conditionals, partially for > difference in handling encryption block (ICE, either as phandle or as > IO address space) but it will further grow for MCQ. Applied to 6.18/scsi-staging, thanks! -- Martin K. Petersen
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