Referred in the documentation as the Software Timer Watchdog (SWT),
the s32g3 has 12 watchdogs. The number of watchdogs is designed to
allow dedicating one watchdog per Cortex-M7/A53 present on the SoC.
Describe them in the device tree.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Cc: Thomas Fossati <thomas.fossati@linaro.org>
---
arch/arm64/boot/dts/freescale/s32g3.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 77ef75bad4be..dabad071bf81 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -670,6 +670,102 @@ stm11: timer@4052c000 {
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ swt0: watchdog@40100000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40100000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt1: watchdog@40104000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40104000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt2: watchdog@40108000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40108000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt3: watchdog@4010c000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x4010c000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt4: watchdog@40200000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40200000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt5: watchdog@40204000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40204000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt6: watchdog@40208000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40208000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt7: watchdog@4020C000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x4020C000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt8: watchdog@40500000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <40500000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt9: watchdog@40504000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40504000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt10: watchdog@40508000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40508000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt11: watchdog@4050c000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x4050c000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
};
timer {
--
2.43.0