On Wed, Jul 30, 2025 at 09:50:18PM +0200, Daniel Lezcano wrote:
> Referred in the documentation as the Software Timer Watchdog (SWT),
> the s32g2 has 7 watchdogs. The number of watchdogs is designed to
> allow dedicating one watchdog per Cortex-M7/A53 present on the SoC.
>
> Describe them in the device tree.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 56 ++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 3e775d030e37..12ce02525ae1 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -566,5 +566,61 @@ stm6: timer@40224000 {
> interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
> +
> + swt0: watchdog@40100000 {
keep order according to hex address.
Frank
> + compatible = "nxp,s32g2-swt";
> + reg = <0x40100000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> +
> + swt1: watchdog@40104000 {
> + compatible = "nxp,s32g2-swt";
> + reg = <0x40104000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> +
> + swt2: watchdog@40108000 {
> + compatible = "nxp,s32g2-swt";
> + reg = <0x40108000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> +
> + swt3: watchdog@4010c000 {
> + compatible = "nxp,s32g2-swt";
> + reg = <0x4010c000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> +
> + swt4: watchdog@40200000 {
> + compatible = "nxp,s32g2-swt";
> + reg = <0x40200000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> +
> + swt5: watchdog@40204000 {
> + compatible = "nxp,s32g2-swt";
> + reg = <0x40204000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> +
> + swt6: watchdog@40208000 {
> + compatible = "nxp,s32g2-swt";
> + reg = <0x40208000 0x1000>;
> + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> + clock-names = "counter", "module", "register";
> + status = "disabled";
> + };
> };
> };
> --
> 2.43.0
>