From: Biju Das <biju.das.jz@bp.renesas.com>

As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.

v2->v3:
 * Added header file linux/io.h
 * Replaced io{read,write}64_rep->{read,write}sq to fix the build error
   reported by the bot.
RFT->v2:
 * Collected tags
 * Fixed the build error reported by the bot.

Biju Das (2):
  mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
  mmc: renesas_sdhi: Enable 64-bit polling mode

 drivers/mmc/host/renesas_sdhi_internal_dmac.c |  3 +-
 drivers/mmc/host/tmio_mmc.h                   | 15 +++++++++
 drivers/mmc/host/tmio_mmc_core.c              | 33 +++++++++++++++++++
 include/linux/platform_data/tmio.h            |  3 ++
 4 files changed, 53 insertions(+), 1 deletion(-)

-- 
2.43.0

Hi Biju,

On Wed, 30 Jul 2025 at 18:46, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.

Thanks for your series!

I believe some of the SoCs that do not support 64-bit accesses, do
support 32-bit accesses. Do you think it would be worthwhile adding
support for that, too?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

> I believe some of the SoCs that do not support 64-bit accesses, do
> support 32-bit accesses. Do you think it would be worthwhile adding
> support for that, too?

We have that already? Check the context after the chunk added to
tmio_mmc_core.c:

        if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
                u32 data = 0;
                u32 *buf32 = (u32 *)buf;
	...

Hi Wolfram,

On Fri, 29 Aug 2025 at 12:26, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > I believe some of the SoCs that do not support 64-bit accesses, do
> > support 32-bit accesses. Do you think it would be worthwhile adding
> > support for that, too?
>
> We have that already? Check the context after the chunk added to
> tmio_mmc_core.c:
>
>         if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
>                 u32 data = 0;
>                 u32 *buf32 = (u32 *)buf;
>         ...

OK, thanks, then I misremembered what exactly is supported and what
is not...
But this is set only on RZ/A1, so my question should be: are there
any other SoCs where TMIO_MMC_32BIT_DATA_PORT should be set?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

> But this is set only on RZ/A1, so my question should be: are there
> any other SoCs where TMIO_MMC_32BIT_DATA_PORT should be set?

I can check if it makes a difference on R-Car boards I have.

On Wed, 30 Jul 2025 at 18:46, Biju <biju.das.au@gmail.com> wrote:
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.
>
> v2->v3:
>  * Added header file linux/io.h
>  * Replaced io{read,write}64_rep->{read,write}sq to fix the build error
>    reported by the bot.
> RFT->v2:
>  * Collected tags
>  * Fixed the build error reported by the bot.
>
> Biju Das (2):
>   mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
>   mmc: renesas_sdhi: Enable 64-bit polling mode
>
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c |  3 +-
>  drivers/mmc/host/tmio_mmc.h                   | 15 +++++++++
>  drivers/mmc/host/tmio_mmc_core.c              | 33 +++++++++++++++++++
>  include/linux/platform_data/tmio.h            |  3 ++
>  4 files changed, 53 insertions(+), 1 deletion(-)
>

The series applied for next, thanks!

Kind regards
Uffe