From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v4: Add self to 'maintainers'
s/gpll0/clk_ref/ in clock-names
s/apss-clock/clock/ in example's node name
v2: Add #interconnect-cells to help enable L3 pll as ICC clock
Add master/slave ids
---
.../bindings/clock/qcom,ipq5424-apss-clk.yaml | 63 +++++++++++++++++++
include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
.../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
3 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
new file mode 100644
index 000000000000..beb6ebe3a773
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APSS IPQ5424 Clock Controller
+
+maintainers:
+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>
+ - Md Sadre Alam <quic_mdalam@quicinc.com>
+ - Varadarajan Narayanan <quic_varada@quicinc.com>
+
+description:
+ The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
+ The RCG and PLL have a separate register space from the GCC.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5424-apss-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference to the XO clock.
+ - description: Reference to the GPLL0 clock.
+
+ clock-names:
+ items:
+ - const: xo
+ - const: clk_ref
+
+ '#clock-cells':
+ const: 1
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#interconnect-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+
+ apss_clk: clock@fa80000 {
+ compatible = "qcom,ipq5424-apss-clk";
+ reg = <0x0fa80000 0x20000>;
+ clocks = <&xo_board>, <&gcc GPLL0>;
+ clock-names = "xo", "clk_ref";
+ #clock-cells = <1>;
+ #interconnect-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
index 77b6e05492e2..0bb41e5efdef 100644
--- a/include/dt-bindings/clock/qcom,apss-ipq.h
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -8,5 +8,11 @@
#define APCS_ALIAS0_CLK_SRC 0
#define APCS_ALIAS0_CORE_CLK 1
+#define APSS_PLL_EARLY 2
+#define APSS_SILVER_CLK_SRC 3
+#define APSS_SILVER_CORE_CLK 4
+#define L3_PLL 5
+#define L3_CLK_SRC 6
+#define L3_CORE_CLK 7
#endif
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
index a770356112ee..afd7e0683a24 100644
--- a/include/dt-bindings/interconnect/qcom,ipq5424.h
+++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -21,4 +21,7 @@
#define MASTER_CNOC_USB 16
#define SLAVE_CNOC_USB 17
+#define MASTER_CPU 0
+#define SLAVE_L3 1
+
#endif /* INTERCONNECT_QCOM_IPQ5424_H */
--
2.34.1On 30/07/2025 10:13, Varadarajan Narayanan wrote:
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm APSS IPQ5424 Clock Controller
> +
> +maintainers:
> + - Sricharan Ramabadhran <quic_srichara@quicinc.com>
> + - Md Sadre Alam <quic_mdalam@quicinc.com>
My v2 comments seems still valid. Your explanation suggests they moved
on, so it is confusing to see them here.
Sricharan and Md Sadre, can you provide Acks for this?
> + - Varadarajan Narayanan <quic_varada@quicinc.com>
> +
> +description:
> + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> + The RCG and PLL have a separate register space from the GCC.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq5424-apss-clk
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Reference to the XO clock.
> + - description: Reference to the GPLL0 clock.
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: clk_ref
> +
> + '#clock-cells':
> + const: 1
> +
> + '#interconnect-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#interconnect-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
> +
> + apss_clk: clock@fa80000 {
This is never called clock@, but clock-controller. Look at any other
qcom bindings or DTS.
Or your cells are incorrect.
Best regards,
Krzysztof
On 7/30/2025 2:32 PM, Krzysztof Kozlowski wrote: > On 30/07/2025 10:13, Varadarajan Narayanan wrote: >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm APSS IPQ5424 Clock Controller >> + >> +maintainers: >> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >> + - Md Sadre Alam <quic_mdalam@quicinc.com> > > My v2 comments seems still valid. Your explanation suggests they moved > on, so it is confusing to see them here. > > Sricharan and Md Sadre, can you provide Acks for this? > Ack. please drop my name. Thanks, Alam.
On 7/30/2025 2:32 PM, Krzysztof Kozlowski wrote: > On 30/07/2025 10:13, Varadarajan Narayanan wrote: >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm APSS IPQ5424 Clock Controller >> + >> +maintainers: >> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >> + - Md Sadre Alam <quic_mdalam@quicinc.com> > > My v2 comments seems still valid. Your explanation suggests they moved > on, so it is confusing to see them here. > > Sricharan and Md Sadre, can you provide Acks for this? > Ack. Please feel free to remove my name. Regards, Sricharan
On 30/07/2025 11:22, Sricharan Ramabadhran wrote: > > > On 7/30/2025 2:32 PM, Krzysztof Kozlowski wrote: >> On 30/07/2025 10:13, Varadarajan Narayanan wrote: >>> +--- >>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm APSS IPQ5424 Clock Controller >>> + >>> +maintainers: >>> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >>> + - Md Sadre Alam <quic_mdalam@quicinc.com> >> >> My v2 comments seems still valid. Your explanation suggests they moved >> on, so it is confusing to see them here. >> >> Sricharan and Md Sadre, can you provide Acks for this? >> > Ack. Please feel free to remove my name. I meant Ack that you still maintain this hardware and bindingd. Best regards, Krzysztof
On 7/30/2025 3:06 PM, Krzysztof Kozlowski wrote: > On 30/07/2025 11:22, Sricharan Ramabadhran wrote: >> >> >> On 7/30/2025 2:32 PM, Krzysztof Kozlowski wrote: >>> On 30/07/2025 10:13, Varadarajan Narayanan wrote: >>>> +--- >>>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Qualcomm APSS IPQ5424 Clock Controller >>>> + >>>> +maintainers: >>>> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >>>> + - Md Sadre Alam <quic_mdalam@quicinc.com> >>> >>> My v2 comments seems still valid. Your explanation suggests they moved >>> on, so it is confusing to see them here. >>> >>> Sricharan and Md Sadre, can you provide Acks for this? >>> >> Ack. Please feel free to remove my name. > > > I meant Ack that you still maintain this hardware and bindingd. I still work on his hardware, but wont be involved in maintaining this binding. Regards, Sricharan
© 2016 - 2025 Red Hat, Inc.