Some USI instances have swconfig offsets that reside over the currently
defined syscon ranges for peric1 and cmgp. Increase their sizes.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
---
arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
index 943e83851..bab77b442 100644
--- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
@@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 {
syscon_peric1: syscon@10720000 {
compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
- reg = <0x10720000 0x2000>;
+ reg = <0x10720000 0x3000>;
};
pinctrl_peric1: pinctrl@10730000 {
@@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 {
syscon_cmgp: syscon@14e20000 {
compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
- reg = <0x14e20000 0x2000>;
+ reg = <0x14e20000 0x3000>;
};
pinctrl_cmgp: pinctrl@14e30000 {
--
2.43.0On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov
<ivo.ivanov.ivanov1@gmail.com> wrote:
>
> Some USI instances have swconfig offsets that reside over the currently
> defined syscon ranges for peric1 and cmgp. Increase their sizes.
>
> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
> arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
> index 943e83851..bab77b442 100644
> --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
> @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 {
>
> syscon_peric1: syscon@10720000 {
> compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
> - reg = <0x10720000 0x2000>;
> + reg = <0x10720000 0x3000>;
Exynos850 TRM says that all System Register instances (in Exynos850
SoC) use 16 KiB (0x4000) of address space for their registers. And I
can see some SYSREG registers actually have offsets over 0x3000. In
reality though all IP cores are aligned by 0x10000. I have a feeling
Samsung does the IP cores integration in the same way for all their
modern Exynos SoCs. It can be actually deduced by looking at the
starting addresses of the nodes in the device tree, they are always
aligned by 0x10000.
Hence I'd recommend doing this:
1. Use either 0x4000 or 0x10000 size (not 0x3000). For the
reference, Exynos850 and gs101 use 0x10000 value.
2. Replace the size values for all sysreg nodes in your device tree
(not only peric1 and cmgp), for consistency and to prevent possible
issues in future.
Also, maybe it'd be better to use "sysreg_" prefix for these node
labels (not "syscon_"), as it's called System Register in TRM. But
that's minor, and probably out of scope for this patch.
> };
>
> pinctrl_peric1: pinctrl@10730000 {
> @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 {
>
> syscon_cmgp: syscon@14e20000 {
> compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
> - reg = <0x14e20000 0x2000>;
> + reg = <0x14e20000 0x3000>;
> };
>
> pinctrl_cmgp: pinctrl@14e30000 {
> --
> 2.43.0
>
>
On 8/2/25 01:11, Sam Protsenko wrote:
> On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov
> <ivo.ivanov.ivanov1@gmail.com> wrote:
>> Some USI instances have swconfig offsets that reside over the currently
>> defined syscon ranges for peric1 and cmgp. Increase their sizes.
>>
>> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
>> ---
> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
>
>> arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
>> index 943e83851..bab77b442 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi
>> @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 {
>>
>> syscon_peric1: syscon@10720000 {
>> compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
>> - reg = <0x10720000 0x2000>;
>> + reg = <0x10720000 0x3000>;
> Exynos850 TRM says that all System Register instances (in Exynos850
> SoC) use 16 KiB (0x4000) of address space for their registers. And I
> can see some SYSREG registers actually have offsets over 0x3000. In
> reality though all IP cores are aligned by 0x10000. I have a feeling
> Samsung does the IP cores integration in the same way for all their
> modern Exynos SoCs. It can be actually deduced by looking at the
> starting addresses of the nodes in the device tree, they are always
> aligned by 0x10000.
>
> Hence I'd recommend doing this:
> 1. Use either 0x4000 or 0x10000 size (not 0x3000). For the
> reference, Exynos850 and gs101 use 0x10000 value.
> 2. Replace the size values for all sysreg nodes in your device tree
> (not only peric1 and cmgp), for consistency and to prevent possible
> issues in future.
Alright, thanks.
>
> Also, maybe it'd be better to use "sysreg_" prefix for these node
> labels (not "syscon_"), as it's called System Register in TRM. But
> that's minor, and probably out of scope for this patch.
Does not matter that much imo, just a label. You could make a patch to
rename it on other trees too.
Best regards,
Ivaylo
>
>> };
>>
>> pinctrl_peric1: pinctrl@10730000 {
>> @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 {
>>
>> syscon_cmgp: syscon@14e20000 {
>> compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
>> - reg = <0x14e20000 0x2000>;
>> + reg = <0x14e20000 0x3000>;
>> };
>>
>> pinctrl_cmgp: pinctrl@14e30000 {
>> --
>> 2.43.0
>>
>>
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